Finding the worst case supply noise excitation methodology for high speed I/O interfaces

Tan, Fern Nee; Lee, Sheng Chyan; Rahman, Fadzilah Abd

doi:10.1109/asqed.2011.6111739

Cited by 2 publications

(1 citation statement)

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“…In addition to the industrial compliance tests above, additional tests were exercised simultaneously in attempt to inject noise into the system and serve as aggressors to the I/ O circuit. 7) To showcase how severe the concurrent test was imposed onto the system for the purpose of this research project, table 1 below compares side by side the difference between industrial product qualification execution and the concurrent stress test setup.…”

Section: Concurrent Stress Test Setupmentioning

confidence: 99%

Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

Tan¹,

Lee²

2013

Journal of the Microelectronics and Packaging Society

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In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

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Section: Concurrent Stress Test Setupmentioning

confidence: 99%