Finding the limit

Abstract

Heterogeneous multi-processors are designed to bridge the gap between performance and energy eeciency in modern embedded systems. is is achieved by pairing Out-of-Order (OoO) cores, yielding performance through aggressive speculation and latency masking, with In-Order (InO) cores, that preserve energy through simpler design. By leveraging migrations between them, workloads can therefore select the best seeing for any given energy/delay envelope. However, migrations introduce execution overheads that can hurt performance if they happen too frequently. Finding the optimal migration frequency is critical to maximize energy savings while maintaining acceptable performance. We develop a simulation methodology that can 1) isolate the hardware eeects of migrations from the sooware, 2) directly compare the performance of diierent core types, 3) quantify the performance degradation and 4) calculate the cost of migrations for each case. To showcase our methodology we run mibench, a microbenchmark suite, and show that migrations can happen as fast as every 100k instructions with liile performance loss. We also show that, contrary to numerous recent studies, hypothetical designs do not need to share all of their internal components to be able to migrate at that frequency. Instead, we propose a feasible system that shares level 2 caches and a translation lookaside buer that matches performance and eeciency. Our results show that there are phases comprising up to 10% that a migration to the OoO core leads to performance beneets without any additional energy cost when running on the InO core, and up to 6% of phases where a migration to the InO core can save energy without aaecting performance. When considering a policy that focuses on improving the energy-delay product, results show that on average 66% of the phases can be migrated to deliver equal or beeer system operation without having to aggressively share the entire memory system or to revert to migration periods ner than 100k instructions.