Finding an Efficient FPGA Implementation of the DES Algorithm to Support the Processor Chip on Smartcard

Kristianti, Veronica Ernita; Wibowo, Eri Prasetyo; Pertiwi, Atit; Afandi, Hamzah; Soerowirdjo, Busono

doi:10.1109/eiconcit.2018.8878519

Cited by 3 publications

(1 citation statement)

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“…Using combinational logic gates to design S-boxes must be uncompromised with achieving high security of algorithm. Kristianti V. E. et al [9] in 2018 proposed DES design by using 8 round algorithms based on a system on chip (SoC). The proposed DES design has been implemented on XC3ES500E FPGA.…”

Section: Literature Reviewmentioning

confidence: 99%

Implementation of Simplified Data Encryption Standard on FPGA using VHDL

Mohammed

2022

KJAR

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In recent years, dramatic changed has been made in communication sector. Due to enormous development in communication devices, globally internet-connected network largely used in all human activities. The security of information has been becoming a major concern for all users and clients, whom depend on network system. The cryptography has played significant role to combat these challenges and improve confidentiality, integrity, and authentication of data communication in the network. The Data Encryption Standard (DES) is one of most familiar type of cryptography and widely used in the modern network system, which has been adopted in encryption and decryption a digital information for several decades. The DES is replaced by a number of new cryptographical methods, which based on DES, like AES and 3DES. In the same time some hardware tools have gained a lot of attention and become interested for researchers and academics to design and implement their model proposals with these hardware-based tools. Therefore, this paper, shows the design of a Simplified Data Encryption Standard (S-DES) by using VHDL language. The design is synthesized, compiled and implemented on the FPGA Altera board, which, consists Quartus II software environment, and Altera Cyclone IV 4CX150FPGA device. The S-DES has been successfully implemented with few numbers of logic elements.

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Section: Literature Reviewmentioning

confidence: 99%