Few Good Frequencies for Power-Constrained Test

Abstract

In the aperiodic clock testing method, power is kept at the specified limit by stretching or contracting the clock periods according to circuit activity. As reported, the test time of power constrained test can be reduced by 40-50%. Considering the capability of the test equipment and simplicity of test program, the number of clock periods should be kept low. In this paper, we give algorithms to find the optimum clock periods. Using the well known relation that the test time equals total energy for the entire test divided by the average power, the kthroot solution maximizes the average power for k test clocks and given maximum power constraint. This solution uses a piece-wise linear approximation for the sorted pseudo-energy profile of test cycles obtained from power estimation and timing analysis tools. For small k, the kth-root solution is optimized by a numerically efficient locally exhaustive search (LES) algorithm. Results show that close to maximum attainable test time reduction is achievable by as few as four to ten selected clocks.