2016
DOI: 10.1016/j.spmi.2015.11.019
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Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: Proposal and investigation

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Cited by 34 publications
(6 citation statements)
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“…Moreover, a ferroelectric model from Miller has been implanted to simulate the effects about high dielectric constants, polarization and hysteresis of the ferroelectric material. The remnant polarization of PZT material [21] is taken as 0.4 μC/cm 2 , saturation polarization as 0.5 μC/cm 2 , and critical electrical field as 0.1 MV/cm in the simulation. It is noteworthy that there are different remnant polarization, saturation polarization and critical electrical field for different ferroelectric materials (such as PZT, SBT, Si:HfO 2 ) and ferroelectric materials with different thickness (such as 20, 15, and 10 nm of Si:HfO 2 ) [26] .…”
Section: Resultsmentioning
confidence: 99%
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“…Moreover, a ferroelectric model from Miller has been implanted to simulate the effects about high dielectric constants, polarization and hysteresis of the ferroelectric material. The remnant polarization of PZT material [21] is taken as 0.4 μC/cm 2 , saturation polarization as 0.5 μC/cm 2 , and critical electrical field as 0.1 MV/cm in the simulation. It is noteworthy that there are different remnant polarization, saturation polarization and critical electrical field for different ferroelectric materials (such as PZT, SBT, Si:HfO 2 ) and ferroelectric materials with different thickness (such as 20, 15, and 10 nm of Si:HfO 2 ) [26] .…”
Section: Resultsmentioning
confidence: 99%
“…To combat the issue of low current driving capability, a number of different technologies have been reported in the literature with gate work function engineering [10] , high-k gate dielectrics engineering [11] , lower bandgap materials employed in source engineering such as germanium (Ge) source [12] and indium arsenide (InAs) source TFETs [13,14] , and some novel structures of TFETs such as gate-all-around triple metal (GAA TM) TFETs [15] , p-n-p-n TFETs [16] , a hetero-junction at the source-channel TFETs [17,18] , a hetero-stacked TFET [19] , electrically doped TFET (ED-TFET) based on polarity control [20] , and so on. Recently, ferroelectric (FE) insulator engineering of TFET has been used due to the fact that the ferroelectric gate dielectric produces a negative capacitance (NC) effect, which leads to the enhanced electric field at the source-channel junction [21][22][23][24] . Therefore, tunneling barrier width for electron injection is reduced.…”
Section: Introductionmentioning
confidence: 99%
“…Use of metal source/drain contact holds the advantage, as it commendably minimizes the issue of higher S/D series resistance and lessens the severe limitations imposed on conventionally implanted S/D. Further, intrinsic Schottky potential barrier of SB-MOSFETs results in greater control of OFF-state leakage current, and the subthreshold slope (SS) of SB-MOSFET has a lower limit of 60 mV/dec at room temperature [ 5 , 6 , 7 , 8 , 9 , 10 ]. Features such as low thermal budget requirements, higher invulnerability to short-channel effects, low source/drain (S/D) parasitic resistances, sub-10 nm gate length scalability and simple fabrication steps make Schottky barrier MOSFETs (SB-MOSFETs) a suitable FET biosensor for the detection of different biomolecules [ 3 , 4 ].…”
Section: Introductionmentioning
confidence: 99%
“…Sumit Kale et al have demonstrated that dopant segregation (DS) at the source-channel junction aids to increase tunneling area, which results in improved device performance with high ON current [ 20 ]. A ferroelectric SB tunnel FET (Fe SB-TFET) with a highly doped pocket at the source/drain and channel interface and gate–drain underlap reduce tunneling barrier width at the source side SB, resulting in improved device performance with low subthreshold swing (SS), reduced ambipolar current and high I ON /I OFF [ 6 ]. Investigation of temperature’s effect on reliability issues of ferroelectric DS SB TFET reveals that the presence of a ferroelectric layer and the resulting negative capacitance effect increases the ON current, achieves highest I ON /I OFF ratio and reduces the SS to 23 mV/dec at 300 K [ 21 ].…”
Section: Introductionmentioning
confidence: 99%
“…However, ambipolarity and lower ON-state current (I ON ) are two major limitations for TFETs [9]. To address these concerns, researchers proposed various device structures such as double-gate, dual material gate, workfunction engineering, material engineering, stacked gate oxide, pocket doping, electrically doped (ED), dielectric pocket, and gate over source overlap, and extended source TFET [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In addition to the above issues, the reliability issues that arise as a result of ITCs developed at the Si-SiO 2 interface due to variations in process, stress, radiation, and the effect of hot carriers are also major concerns [32][33][34][35][36][37][38].…”
Section: Introductionmentioning
confidence: 99%