Ferroelectric FDSOI FET modeling for memory and logic applications

Chatterjee, Swetaki; Kumar, Shubham; Gaidhane, Amol D.; Dabhi, Chetan Kumar; Chauhan, Yogesh Singh; Amrouch, Hussam

doi:10.1016/j.sse.2022.108554

Cited by 12 publications

(13 citation statements)

References 6 publications

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“…To incorporate the impact of physical effects governing the transistor characteristics at cryogenic temperatures, we have modified the existing BSIM-CMG model 41 using the model equation proposed in 42 . The modified BSIM-CMG model accurately captures the charge-voltage characteristics of the FinFETs operating all the way starting from 10 K to 300 K. To accurately model the charges with respect to applied terminal voltages in the FE, we use the dynamic Preisach model 43 , where time-dependent switching operations are modeled with the help of a parallel network of resistor and capacitor.…”

Section: Methodsmentioning

confidence: 99%

“…For accurate Fe-FinFET modeling, we follow the Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) approach in which we couple these two separate models (FE capacitor and FinFET models) and solve the charge conservation and voltage balance at the intrinsic metal node in the MFMIS structure. A detailed description of the model development is given in [42][43][44] . The developed cryogenic aware Fe-FinFET model can solve the Fe-FinFET for a wide range of bias voltages, input pulse sequences, and temperatures.…”

Section: Methodsmentioning

confidence: 99%

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Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

Parihar,

Kumar,

Chatterjee

et al. 2024

Preprint

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The pursuit of large-scale quantum computing has captivated the scientific community, and the potential of cryogenic circuits using mature CMOS technologies represents a significant step forward in this quest. Nevertheless, the operation of circuits at cryogenic temperatures poses significant challenges due to the strict power and timing constraints. These challenges are compounded by the well-known Von Neumann bottleneck that plays a major role in limiting the throughput and energy efficiency of modern computing systems. To overcome such a bottleneck, In-Memory Computing (IMC) is rapidly emerging as a promising solution for creating hardware accelerators that go far beyond Von Neumann principles, offering substantial efficiency improvements. In this work, we investigate the effectiveness of cryogenic brain-inspired hyperdimensional IMC using emerging Ferroelectric (FE) technologies at the 5 nm node. To achieve that, we begin by characterizing commercial 5 nm FinFETs from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model (BSIM-CMG) to accurately reproduce the measurements. Afterward, we incorporate a physics-based FE model within the BSIM-CMG model and calibrated it against FE capacitor measurements to realize Fe-FinFET devices operating from 300 K down to 10 K. Then, as proof of concept, we focus on 1×8 Ternary Content Addressable Memory (TCAM) array that we use to perform the language classification using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of IMC-based TCAM all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

Parihar,

Kumar,

Chatterjee

et al. 2024

Preprint

Self Cite

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“…All the simulations are performed in the commercial SPICE simulator Cadence Spectre. For simulating the FeFET, a Preisach-based model of the FeFET is considered along with the BSIM-IMG model of the transistor 17,18 . To simulate…”

Section: Methods 1fefet-1r Cell Characterizationmentioning

confidence: 99%

“…This forms the basis for the MAC operation.SimulationThe functionality of the proposed in-memory macro is exemplified through simulations. The FeFET is simulated using a Preisach-based model17 of the Ferroelectric capacitor and industry-standard compact model18 of the underlying transistor (for details, see SI). We use 2-bit storage for the FeFET as in measurements, which corresponds to four different V th states.…”

mentioning

confidence: 99%

First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET

Soliman

Chatterjee

Laleni

et al. 2023

Preprint

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Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level FeFET cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variabil21 ity effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based ferroelectric field-effect transistor (FeFET) devices. Unlike tradi23 tional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6%accuracy for handwriting recognition and 91.5%accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achiev28 ing 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional struc31 tural overhead.

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“…Although accurate, TCAD models are resource intensive and thus unsuitable for large-scale circuits and systems simulations. This necessitates a computationally fast and reliable compact model of a FeFET [32], [33].…”

Section: A Our Spice Modeling and Validation Of Fefetmentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

Chatterjee

Thomann

et al. 2023

IEEE Trans. Circuits Syst. I

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Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with > 10 larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET.We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a crosslayer manner is indispensable.

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Ferroelectric FDSOI FET modeling for memory and logic applications

Cited by 12 publications

References 6 publications

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

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