Fermilab silicon strip readout chip for BTEV

Yarema, R.; Hoff, J.; Mekkaoui, A.; Manghisoni, M.; Re, V.; Angeleri, V.; Manfredi, P. F.; Ratti, L.; Speziali, V.

doi:10.1109/nssmic.2004.1462366

Cited by 5 publications

(9 citation statements)

References 8 publications

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“…Since the BLR is ac coupled to the shaper output, contributions to threshold dispersion coming from the previous blocks are suppressed when the BLR is selected. As also discussed in [1], the BLR used in FSSR and FSSR2 is effective in removing the threshold shift due to baseline fluctuations of the signal at the shaper output. Table I shows that the specification σ Qth < 500 e rms is always met in the high gain condition, whereas, at low gain, the BLR has to be selected.…”

Section: A Charge Sensitivity and Threshold Dispersionmentioning

confidence: 96%

“…A discussion of these registers and measurement of their cross section are given in [4]. Since FSSR2 is a mixed signal design with very low noise requirements, care was taken to minimize noise coupling from the digital section to the analog section of the chip, as discussed in [1]. To this purpose, all digital pads use low voltage differential signals (LVDS).…”

Section: A Chip Specifications and Fssr2 Architecturementioning

confidence: 99%

“…Secondly, after the shaper a baseline restorer can be used to cancel baseline shifts at the shaper output which affect the discriminator threshold. As shown in [1], a symmetric BLR is implemented according to the principles discussed in [10]. In FSSR2, the BLR is implemented in all channels in a programmable way, so that it may be used only when the strip signal occupancy is high.…”

Section: B Analog Sectionmentioning

confidence: 99%

“…A general description of the digital section and of the output data format is given in [1] for the FSSR prototype chip and will not be repeated here. In FSSR2, a few changes were made.…”

Section: Digital Sectionmentioning

confidence: 99%

“…FSSR2 is the final step of an R&D effort which began with the design of the prototype chip FSSR [1]. The architecture of both FSSR and FSSR2 is a modified version of that of the FPIX2, the readout chip for the BTeV pixel detector [2].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

Re¹,

Manghisoni²,

Ratti³

et al.

IEEE Nuclear Science Symposium Conference Record, 2005

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Section: A Charge Sensitivity and Threshold Dispersionmentioning

confidence: 96%

Section: A Chip Specifications and Fssr2 Architecturementioning

confidence: 99%

Section: B Analog Sectionmentioning

confidence: 99%

“…A general description of the digital section and of the output data format is given in [1] for the FSSR prototype chip and will not be repeated here. In FSSR2, a few changes were made.…”

Section: Digital Sectionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

Re¹,

Manghisoni²,

Ratti³

et al.

IEEE Nuclear Science Symposium Conference Record, 2005

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Performance of the CLAS12 Silicon Vertex Tracker modules

Antonioli

Boiarinov

Bonneau

et al. 2013

Nuclear Instruments and Methods in Physics Research Section A:

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For the 12 GeV upgrade, the CLAS12 experiment has designed a Silicon Vertex Tracker (SVT) using single sided microstrip sensors fabricated by Hamamatsu. The sensors have graded angle design to minimize dead areas and a readout pitch of 156 µm, with intermediate strip. Double sided SVT module hosts three daisy-chained sensors on each side with full strip length of 33 cm. There are 512 channels per module read out by four Fermilab Silicon Strip Readout (FSSR2) chips featuring data driven architecture, mounted on a rigid-flex hybrid. Modules are assembled on the barrel using unique cantilevered geometry to minimize amount of material in the tracking volume. Design and performance of the SVT modules are presented, focusing on results of electrical measurements.

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Characterization of Silicon Detector Readout Electronics

Jones

2015

J. Inst.

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Configuration and calibration of the front-end electronics typical of many silicon detector configurations were investigated in a lab activity based on a pair of strip sensors interfaced with FSSR2 read-out chips and an FPGA. This simple hardware configuration, originally developed for a telescope at the Fermilab Test Beam Facility, was used to measure thresholds and noise on individual readout channels and to study the influence that different configurations of the front-end electronics had on the observed levels of noise in the system. An understanding of the calibration and operation of this small detector system provided an opportunity to explore the architecture of larger systems such as those currently in use at LHC experiments.

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Fermilab silicon strip readout chip for BTEV

Cited by 5 publications

References 8 publications

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors

Performance of the CLAS12 Silicon Vertex Tracker modules

Characterization of Silicon Detector Readout Electronics

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