Fences in Weak Memory Models

Alglave, Jade; Maranget, Luc; Sarkar, Susmit; Sewell, Peter

doi:10.1007/978-3-642-14295-6_25

Cited by 122 publications

(158 citation statements)

References 22 publications

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“…Assuming SC, at least one of the registers has to hold 1 after the execution of the four statements. However, when executing this program on a multi-core x86 or PowerPC machine, traces are observed in which both registers hold 0 in the final state [4]. This outcome can be caused by the store buffers implemented in these architectures.…”

Section: Fig 1 Litmus Test Illustrating Store Bufferingmentioning

confidence: 99%

“…We identify a large class of data flow analyses-the non-relational ones-that satisfy these conditions. These are guaranteed to be sound for a wide range of modern architectures, namely all those that respect the uniproc axiom as defined in [17,4] and recalled in Sec. 2.…”

Section: Fig 1 Litmus Test Illustrating Store Bufferingmentioning

confidence: 99%

“…Architectures; validity of executions We define formally in [4,17] the notions of architecture and validity of an execution w.r.t. an architecture, but we abstract them away in the present paper, for two reasons.…”

Section: Weak Memory Modelsmentioning

confidence: 99%

“…We also abstract the notion of comparison over architectures of [4,17]. Intuitively, an architecture A 1 is weaker than another one A 2 when the executions valid on A 2 are valid on A 1 .…”

Section: Weak Memory Modelsmentioning

confidence: 99%

“…weak memory models. To describe weak memory models, we use the generic framework of Alglave et al [4,17], which covers a wide range of existing architectures, in particular x86-TSO [20] and a fragment of Power. We summarise the relevant parts of this framework.…”

Section: Introductionmentioning

confidence: 99%

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Soundness of Data Flow Analyses for Weak Memory Models

Alglave

Kroening

Lugton

et al. 2011

Programming Languages and Systems

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Abstract. Modern multi-core microprocessors implement weak memory consistency models; programming for these architectures is a challenge. This paper solves a problem open for ten years, and originally posed by Rinard: we identify sufficient conditions for a data flow analysis to be sound w.r.t. weak memory models. We first identify a class of analyses that are sound, and provide a formal proof of soundness at the level of trace semantics. Then we discuss how analyses unsound with respect to weak memory models can be repaired via a fixed point iteration, and provide experimental data on the runtime overhead of this method.

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Section: Fig 1 Litmus Test Illustrating Store Bufferingmentioning

confidence: 99%

Section: Fig 1 Litmus Test Illustrating Store Bufferingmentioning

confidence: 99%

Section: Weak Memory Modelsmentioning

confidence: 99%

“…We also abstract the notion of comparison over architectures of [4,17]. Intuitively, an architecture A 1 is weaker than another one A 2 when the executions valid on A 2 are valid on A 1 .…”

Section: Weak Memory Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Soundness of Data Flow Analyses for Weak Memory Models

Alglave

Kroening

Lugton

et al. 2011

Programming Languages and Systems

Self Cite

View full text Add to dashboard Cite

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High‐coverage metamorphic testing of concurrency support in C compilers

Windsor

Donaldson

Wickerson

2022

Software Testing Verif & Rel

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SummaryWe present a technique and automated toolbox for randomized testing of C compilers. Unlike prior compiler‐testing approaches, we generate concurrent test cases in which threads communicate using fine‐grained atomic operations, and we study actual compiler implementations rather than abstract mappings. Our approach is (1) to generate test cases with precise oracles directly from an axiomatization of the C concurrency model; (2) to apply metamorphic fuzzing to each test case, aiming to amplify the coverage they are likely to achieve on compiler codebases; and (3) to execute each fuzzed test case extensively on a range of real machines. Our tool, C4, benefits compiler developers in two ways. First, test cases generated by C4 can achieve line coverage of parts of the LLVM C compiler that are reached by neither the LLVM test suite nor an existing (sequential) C fuzzer. This information can be used to guide further development of the LLVM test suite and can also shed light on where and how concurrency‐related compiler optimizations are implemented. Second, C4 can be used to gain confidence that a compiler implements concurrency correctly. As evidence of this, we show that C4 achieves high strong mutation coverage with respect to a set of concurrency‐related mutants derived from a recent version of LLVM and that it can find historic concurrency‐related bugs in GCC. As a by‐product of concurrency‐focused testing, C4 also revealed two previously unknown sequential compiler bugs in recent versions of GCC and the IBM XL compiler.

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ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures

Simner

Flur

Pulte

et al. 2020

Programming Languages and Systems

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Computing relies on architecture specifications to decouple hardware and software development. Historically these have been prose documents, with all the problems that entails, but research over the last ten years has developed rigorous and executable-as-test-oracle specifications of mainstream architecture instruction sets and "user-mode" concurrency, clarifying architectures and bringing them into the scope of programming-language semantics and verification. However, the system semantics, of instruction-fetch and cache maintenance, exceptions and interrupts, and address translation, remains obscure, leaving us without a solid foundation for verification of security-critical systems software. In this paper we establish a robust model for one aspect of system semantics: instruction fetch and cache maintenance for ARMv8-A. Systems code relies on executing instructions that were written by data writes, e.g. in program loading, dynamic linking, JIT compilation, debugging, and OS configuration, but hardware implementations are often highly optimised, e.g. with instruction caches, linefill buffers, out-of-order fetching, branch prediction, and instruction prefetching, which can affect programmer-observable behaviour. It is essential, both for programming and verification, to abstract from such microarchitectural details as much as possible, but no more. We explore the key architecture design questions with a series of examples, discussed in detail with senior Arm staff; capture the architectural intent in operational and axiomatic semantic models, extending previous work on "user-mode" concurrency; make these models executable as test oracles for small examples; and experimentally validate them against hardware behaviour (finding a bug in one hardware device). We thereby bring these subtle issues into the mathematical domain, clarifying the architecture and enabling future work on system software verification.

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Fences in Weak Memory Models

Cited by 122 publications

References 22 publications

Soundness of Data Flow Analyses for Weak Memory Models

Soundness of Data Flow Analyses for Weak Memory Models

High‐coverage metamorphic testing of concurrency support in C compilers

ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures

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