Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

Muta, Hiroki; Suzuki, Shunichi; Yamada, Kazuhiko; Nagahashi, Y.; Tanaka, Tsuyoshi; Okabayashi, H.; Kawamura, Nobuo

doi:10.1109/t-ed.1976.18530

Cited by 25 publications

(3 citation statements)

References 4 publications

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“…As a result of the long access lengths, the drain current shows good saturation with little sign of avalanche induced breakdown for voltages up to V DS = 5 V, significantly higher than the ∼1 V maximum sustainable voltage of the baseline CMOS. Fitting the saturated drain current to a simple square law expression of the form 2 gives the threshold voltage of these depletion mode devices to be −1.1 V.…”

Section: Electrical Measurementsmentioning

confidence: 99%

Impact Ionization in SOI MESFETs at the 32-nm Node

Thornton

Lepkowski

Wilk

2016

IEEE Trans. Electron Devices

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Silicon metal-semiconductor FETs (MESFETs) have been fabricated using a 32-nm silicon-on-insulator (SOI) CMOS technology. The MESFET gates are formed during the self-aligned silicide step and show almost ideal Schottky behavior at low drain voltages. However, an anomalous peak in the reverse gate leakage current appears for drain voltages ≥2 V. The anomalous gate current is attributed to impact ionization generating excess holes that exit the channel through the Schottky contact. An analytical model is used to extract the electron impact ionization rate, α, which agrees with three earlier data sets over nearly four orders of magnitude.Index Terms-Impact ionization, metal-semiconductor FETs (MESFETs), partially depleted (PD), Schottky junction, silicon-on-insulator (SOI).

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Section: Electrical Measurementsmentioning

confidence: 99%

Impact Ionization in SOI MESFETs at the 32-nm Node

Thornton

Lepkowski

Wilk

2016

IEEE Trans. Electron Devices

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“…Device scalability brings an important number of advantages [9]: a) the circuit operational frequency increases with a reduction in gate length, allowing faster circuits; b) the chip area decreases using finger-gate devices instead of closeloop gate structures, enabling higher transistor density in the IC; c) the switching power density remains constant allowing lower power per function or more circuits for the same power; d) the finger-gated transistor approach facilitates the drain sharing technique [10]. This scalable gate approach it is also widely used in GaN HEMTs layouts design [11].…”

Section: The Geometry Layout For the Mesfet With One Finger-gate (Mmentioning

confidence: 99%

4H-SiC MESFET specially designed and fabricated for high temperature integrated circuits

Alexandru

Banu

Godignon

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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Due to its wide bandgap, 4H-SiC is a potential candidate for developing devices capable to operate at elevated temperatures. Nowadays there is an increasing demand for high temperature circuits for drivers of SiC switches applicable to intelligent power management, automotive industry, intelligent sensors for harsh environment, space and aerospace among others. This paper is presenting high temperature experimental results in the 25ºC-300ºC temperature range of the 4H-SiC planar-MESFET specially designed and fabricated for high density SiC integrated circuits implementation.

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“…With the development of ion implantation it was possible to form n-channels on lightly doped p-type substrates without the need for silicon epitaxy. Early work focusing on Si MESFETs for LSI logic used PtSi gate electrodes of length 2 µm patterned by contact printing [10] and as small as 0.25 µm using electron beam lithography [11]. Optimization of the channel doping to minimize substrate parasitics increased f max to 14GHz [12].…”

Section: Silicon Based Mesfetsmentioning

confidence: 99%

SILICON-ON-INSULATOR MESFETs AT THE 45nm NODE

LEPKOWSKI¹,

WILK²,

GHAJAR³

et al. 2013

Selected Topics in Electronics and Systems

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Metal-semiconductor field-effect-transistors (MESFETs) have been fabricated using a commercially available 45nm silicon-on-insulator (SOI) CMOS foundry with no changes to the process flow. Depending upon the layout dimensions, these n-channel, depletion mode devices can be designed for high current drive (ID SAT ≥ 100mA/mm), high operating frequency ( fmax >35 GHz) or enhanced breakdown voltage (VBD >25V). The design flexibility provided by the SOI MESFETs, coupled with the high performance of ULSI CMOS at the 45nm node will enable a variety of analog, RF and mixed signal applications.

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Femto Joule logic circuit with enhancement-type Schottky barrier gate FET

Cited by 25 publications

References 4 publications

Impact Ionization in SOI MESFETs at the 32-nm Node

Impact Ionization in SOI MESFETs at the 32-nm Node

4H-SiC MESFET specially designed and fabricated for high temperature integrated circuits

SILICON-ON-INSULATOR MESFETs AT THE 45nm NODE

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