Feeding Two Cats with One Bowl: On Designing a Fault and Side-Channel Resistant Software Encoding Scheme

Breier, Jakub; Hou, Xiaolu

doi:10.1007/978-3-319-52153-4_5

Cited by 12 publications

(9 citation statements)

References 13 publications

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“…In case of encoding based software countermeasures, there are no works proposing a full cipher evaluation to the best of our knowledge. The closest works to this one evaluate only a single operation on encoded data [18], [17].…”

Section: Countermeasure Evaluation Methodsmentioning

confidence: 99%

“…However, these attacks can be thwarted by a well-designed error correction codes. Some results in this direction are stated in [18], along with the code properties. Similar properties could be derived for fault resilient anticode scheme in case such protection is necessary.…”

Section: Other Fault Analysis Methodsmentioning

confidence: 99%

“…Depending on the encoding scheme design and amount of redundancy, these countermeasures can provide a robust alternative to hardware-based approaches [17]. Breier and Hou [18] showed how to select codes with desired fault properties for protecting binary operations. Theoretical bounds of software encoding countermeasure used in a whole cipher implementation are considered in [19], [20].…”

Section: Countermeasuresmentioning

confidence: 99%

“…2. [18,Definition 9] gives a similar formula as bit flip resistance probability for binary code used in binary operations. The difference is that in [18] the authors do not assume a precharge of a register.…”

Section: Fault Resilient Anticode Schemementioning

confidence: 99%

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On Evaluating Fault Resilient Encoding Schemes in Software

Breier¹,

Hou²,

Liu

2021

IEEE Trans. Dependable and Secure Comput.

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Cryptographic implementations are often vulnerable against physical attacks, fault injection analysis being among the most popular techniques. On par with development of attacks, the area of countermeasures is advancing rapidly, utilizing both hardware-and software-based approaches. When it comes to software encoding countermeasures for fault protection and their evaluation, there are very few proposals so far, mostly focusing on single operations rather than cipher as a whole. In this paper we propose an evaluation framework that can be used for analyzing the effectivity of software encoding countermeasures against fault attacks. We first formalize the encoding schemes in software, helping us to define what properties are required when designing a fault protection. Based on these findings, we develop an evaluation metric that can be used universally to determine the robustness of a software encoding scheme against bit flip faults and instruction skips. We provide a way to select a code according to user criteria and also a dynamic code analysis method to estimate the level of protection of assembly implementations using encoding schemes. Finally, we verify our findings by implementing a block cipher PRESENT, protected by encoding scheme based on anticodes, and provide a detailed evaluation of this implementation using different codes.

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Section: Countermeasure Evaluation Methodsmentioning

confidence: 99%

Section: Other Fault Analysis Methodsmentioning

confidence: 99%

Section: Countermeasuresmentioning

confidence: 99%

Section: Fault Resilient Anticode Schemementioning

confidence: 99%

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On Evaluating Fault Resilient Encoding Schemes in Software

Breier¹,

Hou²,

Liu

2021

IEEE Trans. Dependable and Secure Comput.

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“…On the other side, software routines generally run on a known microcontroller's architecture where protection against fault injection attacks is limited to the microcontroller's default hardware countermeasures and the scheme-specific www.ijacsa.thesai.org software countermeasures [13]. Recent works, try to fill this gap by combining software SCA and FA countermeasures in general purpose microcontroller [14].…”

Section: A Fault Injection Attacks On Microcontrollersmentioning

confidence: 99%

An RTOS-based Fault Injection Simulator for Embedded Processors

Alimi¹,

Lahbib²,

Machhout³

et al. 2017

ijacsa

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Abstract-Evaluating embedded systems vulnerability to faults injection attacks has gained importance in recent years due to the rising threats they bring to chips security. The task is particularly important for micro-controllers since they have lower resistance to fault attacks compared to hardware-based cryptosystems. This paper reviews recent embedded fault injection simulators from literature and presents an embedded high-level fault injection mechanism based on a Real-Time Operating System (RTOS). The approach aims to be architecture-independent and portable to 32-bit microcontrollers and embedded processors. The proposed mechanism, primarily targets realistic fault attack scenarios on memory locations, is adapted to timed and event-based fault injection. A Differential Fault Attack (DFA) was mounted on a popular ARM-based micro-controller running FreeRTOS to illustrate the proposed mechanism. The aim is also to bridge the embedded fault injection simulation mechanism efficiently to a computerbased cryptanalysis and to highlight the importance of physically protecting the memory and integrating data-specific countermeasures.

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Fault Attack

Baksi

2022

Computer Architecture and Design Methodologies

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Feeding Two Cats with One Bowl: On Designing a Fault and Side-Channel Resistant Software Encoding Scheme

Cited by 12 publications

References 13 publications

On Evaluating Fault Resilient Encoding Schemes in Software

On Evaluating Fault Resilient Encoding Schemes in Software

An RTOS-based Fault Injection Simulator for Embedded Processors

Fault Attack

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