Features of phonon-limited electron mobility behavior of double-gate field-effect transistor with (111) Si surface channel

Abstract

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Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels

“…With regard to 0;intra , however, a difference between SG and DG MOSFETs appears at medium-to-high E eff ; DG SOI MOSFETs have a higher 0;intra than SG SOI MOSFETs. As a result, DG SOI MOSFETs have higher overall mobility than SG SOI MOSFETs at medium-to-high E eff at 300 K. 15) At 77 K, the DG SOI MOSFETs exhibit greatly enhanced 0;intra and 0 at medium-to-high E eff , which strongly indicates that the entire mobility component 0 is strongly dominated by the intra-subband scattering events of electrons. It is anticipated that this aspect of the behavior of mobility component 0 stems from the very high occupation of the lowest subband as shown in Fig.…”

“…Electron effective mass values in Si (X band) assumed in simulations. 15,16,25) Si( 001 Figure 3 shows the relative magnitude of phonon-limited mobility ( ph = ph,DG(001) ) as a function of temperature for various surface orientations and device structures, where T SOI ¼ 6 nm, and E eff ¼ 1 MV/cm, and ph,DG(001) denotes the phonon-limited electron mobility on the (001) Si surface of the DG SOI MOSFET. These conditions are intentionally selected because electron mobility takes a maximum value at approximately 6 nm regardless of the temperature for both surfaces.…”

“…Doping levels (N A ) in the SOI layer and Si substrate are taken to be 5 Â 10 15 cm À3 . 15) We simulated the phonon-limited inversion-layer electron mobility on the (111) and (001) Si surfaces of SG and DG SOI MOSFET's at various temperatures through 1D self-consistent simulations and the relaxation time approximation. 3,4,[21][22][23] As assumed by many others, the following expression is used to determine the relaxation time due to the acoustic phonon-scattering process: [24][25][26][27]…”

“…where m c;i is the conductivity effective mass of electrons at the specific ith subband of each conduction band, i ðEÞ is the relaxation time of phonon scattering, and E i is the ith subband energy level of each conduction band. Since the total mobility is determined by averaging each subband mobility weighted by its fraction of electrons ( f i ), the phonon-limited electron mobility ( ph ) is calculated using the following equation: 3,4,15) Table I. Electronic band parameter values assumed in simulations.…”

“…[11][12][13][14] We have already demonstrated, through one-dimensional (1D) self-consistent calculations and relaxation time approximations, that the phonon-limited inversion-layer electron mobility on the (111) Si surface of the DG SOI MOSFET at room temperature is superior to that of the SG SOI MOSFET when the SOI layer thickness (T SOI ) is approximately 5 nm. 15,16) We also evaluated the phononlimited inversion-layer electron mobility on the (001) and (111) Ge surfaces of a germanium-on-insulator (GOI) MOSFET at room temperature from the viewpoint of future device applications. 17) It was revealed that the phononlimited electron mobility of the GOI MOSFET has similar transport characteristics owing to its similar band structure.…”