Feasibility study for thermal conductivity simulation by coupling between admittance matrix method and finite elemental method

Temperature gradient‐aware thermal simulator for three‐dimensional integrated circuits

“…Accordingly, the explicit method and the FVM have been utilised to perform the temporal TA in this study. Thus, (9) can be reformulated according to the FVM and the explicit method as follows: (see (10))…”

“…Wang et al [9] presented an effective 3D transient thermal simulator that entailed using the alternating direction implicit method, based on the FDM, for estimating the temperature in a 3D environment. The method by Yoshinari et al [10] presented a combination of the finite‐element method (FEM) and admittance matrix method for simulating the thermal conductivity of large‐scale power electronic systems. Zjajo et al [11] presented an effective methodology based on a discontinuous Galerkin FEM for the TA of a 3D multilayer substrate IC.…”

“…Thermal analysis (TA) techniques at architectural level are proposed to predict the temperatures of ICs at the early stages of IC design, through heat transfer analysis using information on ICs, such as floorplan and power consumption [6][7][8][9][10][11][12][13][14][15]. When integrated with thermal management techniques such as task migration, power gating, and dynamic voltage and frequency scaling in virtual platforms to co-design, co-simulate, and co-verify software and hardware by the methodology of electronic system-level design at the early stages of IC design [16], the temperatures of the hot spots can effectively be minimised, thus reducing the cost of IC design as well.…”

“…Nowadays, the TA techniques integrated into thermal simulators of ICs have been studied in [6][7][8][9][10][11][12][13][14][15]. However, the TA in [6][7][8][9][10][11][12][13][14][15] nearly neglects the temperature-dependent factors. Hence, this paper proposes a temperature gradient-aware thermal simulator for 3D ICs (called 3D-TarGA) at the architectural level to obtain effective thermal profiles at the early stages of IC design.…”