Feasibility and performance region modeling of analog and digital circuits

Harjani, Ramesh; Shao, Jianfeng

doi:10.1007/bf00713977

Cited by 58 publications

(21 citation statements)

References 10 publications

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“…In [18], radial-basis-functions model the feasibility, and the performance of subblocks at all levels of the hierarchy. More recently, [9] uses Support Vector Machines and treats the problem as merely a classification problem, with performance values as inputs and feasible y/n as the output.…”

Section: Feasibility Modeling Bottom-up Plus Tdcdmentioning

confidence: 99%

Performance space modeling for hierarchical synthesis of analog integrated circuits

Gielen

McConaghy

Eeckelaert

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient methods that can handle design hierarchy, in terms of both performance estimation and hierarchical design optimization method. This paper discusses and compares recent developments in this area, with special emphasis on automated modeling and on multi-objective bottom-up hierarchical design.

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Section: Feasibility Modeling Bottom-up Plus Tdcdmentioning

confidence: 99%

Performance space modeling for hierarchical synthesis of analog integrated circuits

Gielen

McConaghy

Eeckelaert

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…Compared with the first modeling approach, the second one is more efficient and flexible. Recently, several new methodologies, including radial basis approximation [8], [9] and data mining [10], etc., have been developed to efficiently approximate the high-dimensional nonlinear functions for analog circuit modeling. These techniques mainly focus on the problem of top-down design/synthesis, where the dimension of analog design space, i.e., the number of free variables, is extremely large.…”

Section: Introductionmentioning

confidence: 99%

Behavioral modeling for analog system-level simulation by wavelet collocation method

Zeng

Zhou³

et al. 2003

IEEE Trans. Circuits Syst. II

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In this paper, we propose a wavelet collocation method with nonlinear companding to generate behavioral models for analog circuits at the system level. During the overall process of circuit modeling, nonlinear function approximation is an important issue to accurately capture the nonideal input-output relations of analog circuit blocks. While a great number of previous research works focus on the high-dimensional top-down design/synthesis model, which involves large analog design spaces, this paper primarily concentrates on the bottom-up verification model requiring both simple representation and high accuracy. Taking advantage of the local support of wavelet bases, a nonlinear companding method is developed to control the modeling error distribution based on system-level simulation requirements. It, in turn, significantly improves the simulation efficiency at the system level. To demonstrate the promising features of the proposed method, two circuit examples, a fourth-order switched-current filter and a voltage-controlled oscillator, are employed to build the behavioral models.

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“…al in [2] proposed adaptive sampling techniques to build an accurate feasibility macromodel. The authors propose to place more samples in all regions which are inaccurate.…”

Section: Related Workmentioning

confidence: 99%

“…Adaptive sampling techniques minimize the modeling error by placing more samples in the inaccurate regions of the design space as in [1], [2]. However, a miniscule fraction of the entire design space contains feasible designs.…”

Section: Introductionmentioning

confidence: 99%

“…This gain in speed in performance estimation allows circuit sizing tools to explore several design alternatives in a relatively small amount of time. Several techniques [1], [2] have been proposed to improve the accuracy of macromodels by judicious, yet adequate, sampling of the design space. However, the question really is are the macro-models accurate enough to replace a numerical simulator in a circuit synthesis loop?…”

Section: Introductionmentioning

confidence: 99%

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Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits

Agarwal¹,

Vemuri²

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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Accurate performance modeling is essential for its usage in a circuit synthesis flow. Only a small fraction of the entire design space is occupied by designs with meaningful behavior and performance. In this work, we have focussed on modeling these feasible regions accurately in contrast with modeling the entire design space. Macromodels for the feasible regions were built hierarchically until the desired accuracy was achieved. An accuracy driven synthesis methodology is proposed to guide the identification of the feasible regions and dynamically enhance the performance of the macromodels. Dynamic performance modeling ensures true convergence of our synthesis approach as opposed to existing static macromodel based techniques. We applied the proposed methodology for modeling and synthesis of several analog and RF circuits and the results demonstrate that our approach yields highly accurate design solutions in a much smaller time compared to simulation based approaches.

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Feasibility and performance region modeling of analog and digital circuits

Cited by 58 publications

References 10 publications

Performance space modeling for hierarchical synthesis of analog integrated circuits

Performance space modeling for hierarchical synthesis of analog integrated circuits

Behavioral modeling for analog system-level simulation by wavelet collocation method

Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits

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