2004
DOI: 10.1109/tns.2004.832895
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FE-I2: a front-end readout chip designed in a commercial 0.25-/spl mu/m process for the ATLAS pixel detector at LHC

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Cited by 26 publications
(21 citation statements)
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“…A Pixel module [13,14] consists of a single silicon wafer with an array of 50×400 µm 2 pixels that are read out by 16 chips [15]. The active area of each module is ∼ 60.8 × 16.4 mm 2 .…”
Section: Setup Data Samples and Trackingmentioning
confidence: 99%
“…A Pixel module [13,14] consists of a single silicon wafer with an array of 50×400 µm 2 pixels that are read out by 16 chips [15]. The active area of each module is ∼ 60.8 × 16.4 mm 2 .…”
Section: Setup Data Samples and Trackingmentioning
confidence: 99%
“…The challenge in the design of the front-end pixel electronics [13] can be summarized by the following requirements: low power (< 50µW per pixel), low noise and threshold dispersion (together < 200e), zero suppression in every pixel, on-chip hit buffering, and small time-walk to be able to assign the hits to their respective LHC bunch crossing. The pixel groups at the LHC have reached these goals in several design iterations using first radiation-soft prototypes, then dedicated radhard designs, and finally using deep submicron technologies.…”
Section: Radiation Hard Hybrid Pixel Detectors For the Lhcmentioning
confidence: 99%
“…Their design was similar to that of the final front-end electronics for ATLAS Pixel [14,15]. In each front-end chip, 2880 channels are arranged into 18 columns by 160 rows.…”
Section: Front-end Electronicsmentioning
confidence: 99%