FBDtoVerilog 2.0: An Automatic Translation of FBD into Verilog to Develop FPGA

Lee, Dong-Ah; Kim, Eui-Sub; Yoo, Junbeom; Lee, Jang-Soo; Choi, Jong Gyun

doi:10.1109/icisa.2014.6847402

Cited by 4 publications

(4 citation statements)

References 5 publications

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“…As an alternative, we are also planning to develop our own translation rules and translator like our research about 'FBDtoVerilog' [24], [8].…”

Section: A Fbdtocadencesmvmentioning

confidence: 99%

“…In order to reduce the risk and preserve the experience and knowledge, we did propose a hybrid development process [7] which uses the 'FBDtoVerilog' translator. The 'FBDtoVerilog' [8] mechanically translates FBD(Function Block Diagram) programs of the PLC-based development into Verilog programs of the FPGA-based development, while preserving behavioral equivalence. It is also required to demonstrate its safety and correctness sufficiently before being used in earnest.…”

Section: Introductionmentioning

confidence: 99%

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A Technique for Demonstrating Safety and Correctness of Program Translators: Strategy and Case Study

Yoo

Choi

Lee

2014

2014 IEEE International Symposium on Software Reliability Engineering Workshops

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The safety and correctness demonstration of program translators plays a critical role in software certification of digital I&C (Instrumentation & Control) systems in nuclear power plants. This paper proposes a strategy for the demonstration of the FBDtoVerilog translator, which translates FBD programs into Verilog programs to synthesize FPGAs. It uses safety case to explain the strategy precisely and also implemented several supporting tools to derive evidences efficiently. A case study of a Korean nuclear power plant found the efficiency of the proposed demonstration strategy and supporting tools.

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“…As an alternative, we are also planning to develop our own translation rules and translator like our research about 'FBDtoVerilog' [24], [8].…”

Section: A Fbdtocadencesmvmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Technique for Demonstrating Safety and Correctness of Program Translators: Strategy and Case Study

Yoo

Choi

Lee

2014

2014 IEEE International Symposium on Software Reliability Engineering Workshops

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“…The Verilog program translated by FBDtoVerilog 2.0/ 2.1 [72,73] and the VHDL program by FBDtoVHDL 1.0 [74] are the starting point of the fully-automated FPGA synthesis procedure provided by commercial EDA tools, as shown in Fig. 7.…”

Section: The Fpga Implementation Phasementioning

confidence: 99%

“…FBDtoC [71] translates the FBD into a behaviorally-equivalent C program for PLC, while FBDtoVerilog 2.0/2.1 [72,73] transforms it into a Verilog program for FPGA. FBDtoVHDL [74] transforms the FBD into a VHDL program, too.…”

Section: B the Design Phasementioning

confidence: 99%

NuDE 2.0: A Formal Method-based Software Development, Verification and Safety Analysis Environment for Digital I&Cs in NPPs

Kim¹,

Lee²,

Jung³

et al. 2017

Journal of Computing Science and Engineering

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NuDE 2.0 (Nuclear Development Environment 2.0) is a formal-method-based software development, verification and safety analysis environment for safety-critical digital I&Cs implemented with programmable logic controller (PLC) and field-programmable gate array (FPGA). It simultaneously develops PLC/FPGA software implementations from one requirement/design specification and also helps most of the development, verification, and safety analysis to be performed mechanically and in sequence. The NuDE 2.0 now consists of 25 CASE tools and also includes an in-depth solution for indirect commercial off-the-shelf (COTS) software dedication of new FPGA-based digital I&Cs. We expect that the NuDE 2.0 will be widely used as a means of diversifying software design/implementation and model-based software development methodology.

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NuDE 2.0: A model-based software development environment for the PLC & FPGA based digital systems in nuclear power plants

Yoo

Kim

Lee

et al. 2014

2014 International Symposium on Integrated Circuits (ISIC)

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NuDE 2.0 (Nuclear Development Environment) is a model-based software development environment for safetycritical digital systems in nuclear power plants. It makes possible to develop PLC-based systems as well as FPGA-based systems simultaneously. The NuDE starts from a formal requirement specification specialized for the nuclear domain, and synthesizes C and Verilog codes for PLC and FPGA, respectively, through a series of model transformation. It also provides various methods for formal verification and safety analysis with support of automatic CASE tools. We expect that the NuDE can be adopted as an effective method of bridging the gap between the PLC and FPGA-based developments as well as a means of gaining diversity.

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FBDtoVerilog 2.0: An Automatic Translation of FBD into Verilog to Develop FPGA

Cited by 4 publications

References 5 publications

A Technique for Demonstrating Safety and Correctness of Program Translators: Strategy and Case Study

A Technique for Demonstrating Safety and Correctness of Program Translators: Strategy and Case Study

NuDE 2.0: A Formal Method-based Software Development, Verification and Safety Analysis Environment for Digital I&Cs in NPPs

NuDE 2.0: A model-based software development environment for the PLC & FPGA based digital systems in nuclear power plants

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FBDtoVerilog 2.0: An Automatic Translation of FBD into Verilog to Develop FPGA

Cited by 4 publications

References 5 publications

A Technique for Demonstrating Safety and Correctness of Program Translators: Strategy and Case Study

A Technique for Demonstrating Safety and Correctness of Program Translators: Strategy and Case Study

NuDE 2.0: A Formal Method-based Software Development, Verification and Safety Analysis Environment for Digital I&Cs in NPPs

NuDE 2.0: A model-based software development environment for the PLC &amp; FPGA based digital systems in nuclear power plants

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NuDE 2.0: A model-based software development environment for the PLC & FPGA based digital systems in nuclear power plants