Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems

Xia, Lixue; Liu, Mengyun; Ning, Xuefei; Chakrabarty, Krishnendu; Wang, Yu

doi:10.1109/tcad.2018.2855145

Cited by 38 publications

(17 citation statements)

References 34 publications

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“…Therefore, poor switching endurance could indirectly lead to low number of conductance states or even failure such as stuck at fault where only one conductance state exists. [76] The impossibility to update the conductance decreases the ANN accuracy, [59] even more so for ex situ training where weights are supposed to be mapped on working devices. The same analysis can be made with the device-to-device variability parameter, which becomes a problem only if this variability concerns critical device characteristics like cycle-to-cycle variability [66] or the overall asymmetry of conductance variation.…”

Section: Box 1 Analysis Of Nonideal Parameters Of Rs Memories That Imentioning

confidence: 99%

In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives

Amirsoleimani

Alibart

Yon

et al. 2020

Advanced Intelligent Systems

118

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Fabien Alibart received a Ph.D. in material science from University of Picardie Jules Verne, France, in 2008. He joined IEMN-CNRS in 2012 as a permanent researcher where he worked on the concepts of neuromorphic/bioinspired computing with emerging memory technologies. He is now with LN2-3IT CNRS as a researcher participating in the join laboratory program between France and Quebec (UMI-CNRS) where he is developing neuromorphic hardware for a variety of applications, from edge computing to brain-machine interfaces.

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Section: Box 1 Analysis Of Nonideal Parameters Of Rs Memories That Imentioning

confidence: 99%

In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives

Amirsoleimani

Alibart

Yon

et al. 2020

Advanced Intelligent Systems

118

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“…The effect of faults occurring in the storage of the input is also considered in [13], and [14] proposes on-chip learning for support-vector machines, while decreasing the learning effort using active learning. Finally, a slightly different problem is considered in [15], [16], where the network is trained to compensate for known defect locations.…”

Section: Related Workmentioning

confidence: 99%

Training Modern Deep Neural Networks for Memory-Fault Robustness

Hacene

Leduc-Primeau

Soussia

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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Because deep neural networks (DNNs) rely on a large number of parameters and computations, their implementation in energy-constrained systems is challenging. In this paper, we investigate the solution of reducing the supply voltage of the memories used in the system, which results in bit-cell faults. We explore the robustness of state-of-the-art DNN architectures towards such defects and propose a regularizer meant to mitigate their effects on accuracy. Our experiments clearly demonstrate the interest of operating the system in a faulty regime to save energy without reducing accuracy.

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“…Reliability analysis, post fabrication test, design-for-test and design-for-reliability are commonly used when dealing with traditional computing architectures, however, they are not common practice when dealing with neuromorphic structures. In this context, there are several research works focusing on the fault tolerance (and how it can be improved) of artificial neural networks (ANNs) [44], on boosting fault tolerance of hardware implemented neural accelerators [45], and even on the effect of fabrication-induced variability of memristive devices on the behavior of deep networks [46] and SNNs [47]. These papers show that faulty neurons have stronger impact on the neural network's behavior than faulty synapses.…”

Section: Neuromorphic Computing Paradigms and Test/reliability Ismentioning

confidence: 99%

Rebooting Computing: The Challenges for Test and Reliability

Bosio

O’Connor

Rodrigues

et al. 2019

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Today's computer architectures and semiconductor technologies are facing major challenges making them incapable to deliver the required features (such as computer efficiency) for emerging applications. Alternative architectures are being under investigation in order to continue deliver sustainable benefits for the foreseeable future society at affordable cost. These architectures are not only changing the traditional computing paradigm (e.g., in terms of programming models, compilers, circuit design), but also setting up new challenges and directions on the way these architectures should be tested to guarantee the required quality and reliability levels. This paper highlights the major open questions regarding test and reliability of three emerging computing paradigms being approximate computing, computation-in-memory and neuromorphic computing.

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Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems

Cited by 38 publications

References 34 publications

In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives

In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives

Training Modern Deep Neural Networks for Memory-Fault Robustness

Rebooting Computing: The Challenges for Test and Reliability

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