Fault-Tolerant Design of the IBM Power6 Microprocessor

Reick, Kevin; Sanda, P. N.; Swaney, S. B.; Kellington, Jeffrey W.; Mack, Michael J.; Floyd, Michael S.; Henderson, Daniel A.

doi:10.1109/mm.2008.22

Cited by 60 publications

(25 citation statements)

References 9 publications

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“…R 2 varies between 0 and 1, computed by (15). Larger R 2 represents a better predictive fit, indicating that the corresponding performance metric correlates well with L1D AVF.…”

Section: Comparison Of L1d Avf Predictive Methodsmentioning

confidence: 95%

“…Furthermore, AVF prediction/estimation mechanisms have been introduced and incorporated into the dynamic fault tolerant system design to make tradeoffs between reliability and performance [11][12][13] . To our knowledge, they focused on a few given micro-architecture structures, e.g., issue queue (IQ), reorder buffer (ROB) and register file, but Parity and error correction codes (ECC) based protection schemes have been widely adopted in modern microprocessors and systems [14][15][16][17][18][19][20][21] . Although ECC protection techniques enable the hardware to maintain a high level of reliability, they bring about significant area, performance and power costs.…”

Section: Introductionmentioning

confidence: 99%

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Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

Cheng

Zhang

2011

J. Comput. Sci. Technol.

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With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor (AVF) has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures (i.e., issue queue, reorder buffer). Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes (ECC). However, protecting caches closer to the processor (i.e., L1 data cache (L1D)) using ECC could result in high overhead. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection. Therefore, designing AVF-aware ECC is attractive for designers to balance among performance, power and reliability for cache, especially at early design stage. In this paper, we improve the methodology of cache AVF computation and develop a new AVF estimation framework, soft error reliability analysis based on SimpleScalar. Then we characterize dynamic vulnerability behavior of L1D and detect the correlations between L1D AVF and various performance metrics. We propose to employ Bayesian additive regression trees to accurately model the variation of L1D AVF and to quantitatively explain the important effects of several key performance metrics on L1D AVF. Then, we employ bump hunting technique to reduce the complexity of L1D AVF prediction and extract some simple selecting rules based on several key performance metrics, thus enabling a simplified and fast estimation of L1D AVF. Based on the simplified and fast estimation of L1D AVF, intervals of high L1D AVF can be identified online, enabling us to develop the AVF-aware ECC technique to reduce the overhead of ECC. Experimental results show that compared with traditional ECC technique which provides complete ECC protection throughout the entire lifetime of a program, AVF-aware ECC technique reduces the L1D access latency by 35% and saves power consumption by 14% for SPEC2K benchmarks averagely.

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“…R 2 varies between 0 and 1, computed by (15). Larger R 2 represents a better predictive fit, indicating that the corresponding performance metric correlates well with L1D AVF.…”

Section: Comparison Of L1d Avf Predictive Methodsmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

Cheng

Zhang

2011

J. Comput. Sci. Technol.

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“…Recovery from hard errors in microprocessor systems is demonstrated by the IBM POWER high-performance critical server platform [111,112]. These microprocessors are capable of restoring operation following permanent hardware failures in memory and clock signal sub-components by invoking redundant hardware in an autonomous fashion that would otherwise require system downtime.…”

Section: Surveymentioning

confidence: 99%

“…A self-repairing mechanism is also applied to the master oscillator of the main board of IBM POWER and Intel Itanium processors [112,[115][116][117], whereby a redundant oscillator is immediately initiated in the event of failure. This requires dynamic self-synchronisation between the two oscillators to ensure seamless switchover.…”

Section: Surveymentioning

confidence: 99%

Self-healing and self-repairing technologies

Frei

McWilliam

Derrick

et al. 2013

Int J Adv Manuf Technol

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This article reviews the existing work in selfhealing and self-repairing technologies, including work in software engineering, materials, mechanics, electronics, MEMS, self-reconfigurable robotics, and others. It suggests a terminology and taxonomy for self-healing and selfrepair, and discusses the various related types of other self-* properties. The mechanisms and methods leading to selfhealing are reviewed, and common elements across disciplines are identified.

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“…Typical hardware redundancy such as chip-level Dual Modular Redundancy (DMR) [8] may introduce great area and power overhead. As a famous example, the IBM Power 6 microprocessor integrates two homogenous cores.…”

Section: Introductionmentioning

confidence: 99%

The Impact of MBUs on the Reliability of Rollback Recovery Circuits

Huang

Liang

2009

2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis

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With technology scaling, radiation induced soft errors have become a serious issue for both aero and terrestrial applications. To mitigate soft errors induced by radiation, rollback recovery is one of the most commonly used techniques. In this paper, a model that deals with Multiple Bit Upsets (MBUs) is proposed to study the impact of MBUs on the reliability of rollback recovery circuits, by calculating the soft error rate of 180nm devices. The simulations at ground level and at high latitude show that the rollback recovery circuits suffering MBUs can effectively mitigate soft errors.

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Fault-Tolerant Design of the IBM Power6 Microprocessor

Cited by 60 publications

References 9 publications

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design

Self-healing and self-repairing technologies

The Impact of MBUs on the Reliability of Rollback Recovery Circuits

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