Fault-tolerant computation within complex FIR filters

Abstract

In this paper we propose an architecture for the implementation of fault-tolerant computation within a high throughput multirate equalizer for an asymmetrical wireless LAN. The area overhead is minimized by exploiting the algebraic structure of the Modulus Replication Residue Number System (MRRNS). We demonstrate that for our system the area cost to correct a fault in a single computational channel is 82.7%. Generalized results for single error correction showing significant area savings are also presented.

A Fault-Tolerant Modulus Replication Complex FIR Filter

“…This system requires 2n + 1 computational channels, which results in a ( n + 1) x ( 2n + 1) array of MAC cells for the polynomial evaluation map, and a ( 2n + 1) x ( 2n + 1) array for the interpolation map. The area of the original system can be approximated as [27]: A0 = 6n 2 + 13.5n + 5.9 + 2.6hn + 1.3h ( 4.1) To correct up to one error, 2n + 3 computational channels are required. The polynomial evaluation map is expanded to be a ( n + 1) x (2n + 3) array of MAC cells, and the interpolation map will use ( 2n + 3) arrays consisting of ( 2n + 2) x ( 2n + 2) MAC cells.…”

“…); end lfsr3 1; architecture behavior of lfsr3 1 is signal reg: std-logic-vector( 30 downto 0); begin output <= reg; process( SYScik) begin if rising_edge(SYSclk) then if( reset = ' 0') then reg <= ( others => T); elsif( shift_en = ' 0') then reg <= reg; else reg (7) <= reg( 8); reg (6) <= reg (7); reg( 5) <= reg (6) xor reg(0); reg (4) <= reg(5); reg(3) <= reg(4); reg(2) <= reg(3); reg(1) <= reg(2); reg(0) <= reg(1 (30) xor reg(0); reg (28) <= reg (29); reg (27) <= reg (28) xor reg(0); reg (26) <= reg (27) xor reg(0); reg (25) <= reg (26); reg (24) <= reg (25); reg (23) <= reg (24) xor reg(0); reg (22) <= reg (23) xor reg(0); reg (21) <= reg (22); reg (20) <= reg (21) xor reg(0); reg (19) <= reg (20); reg (18) <= reg (19) xor reg(0); reg (17) <= reg (18) xor reg(0); reg (16) <= reg (17) xor reg(0); reg (15) <= reg (16); reg (14) <= reg (15) xor reg(0); reg (13) &...…”

“…reg(30) <= reg(0); reg(29) <= reg(30) xor reg(0); reg(28) <= reg(29) xor reg(0); reg(27) <= reg(28); reg(26) <= reg(27); reg(25) <= reg(26); reg(24) <= reg(25) xor reg(0); reg(23) <= reg(24); reg(22) <= reg(23) xor reg(0); reg(21) <= reg(22); reg(20) <= reg(21) xor reg(0); reg(19) <= reg(20) xor reg(0); reg(18) <= reg(19); reg(17) <= reg(18); reg(16) <= reg(17) xor reg(0); reg(15) <= reg(16); reg(14) <= reg(15); reg(13) <= reg(14) xor reg(0); reg(12) <= reg(13) xor reg(0); reg(11) <= reg(12); reg(10) <= reg(11); reg(9) <= reg(10) xor reg(0); reg(8) <= reg…”