Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits

Zheng, Yi-Xue; Kan, Po-Ping; Chen, Liangbi; Hsieh, Kai-Yang; Cheng, Bo-Chuan; Li, Katherine Shu-Min

doi:10.1109/socc.2011.6085088

Cited by 1 publication

(2 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The authors of [12] investigated permanent flaws in the Network Interface (NI) of an application-specific 3D NoC design. They took into account a single fault that could occur in the NI and used spare NIs as part of the fault-tolerance.…”

Section: Literature Surveymentioning

confidence: 99%

See 1 more Smart Citation

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

et al. 2021

View full text Add to dashboard Cite

Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, faulttolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant applicationspecific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a tablebased fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) -4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

show abstract

Section: Literature Surveymentioning

confidence: 99%

“…The results show that the overhead in power consumption is minimal when compared to other approaches. However, the approach proposed by the authors [12] has taken into account NI failures and is limited to 3D NoC. The authors of [13] presented a fault-tolerant ASNoC for link faults based on Integer Linear Programming (ILP).…”

Section: Literature Surveymentioning

confidence: 99%