Fault Tolerance Techniques for Systolic Arrays

Abraham, Robin; Banerjee,; Chen, Chien-Yi; Fuchs, Alexandra; Kuo, Sy‐Yen; Reddy, Narasimha

doi:10.1109/mc.1987.1663621

Cited by 88 publications

(9 citation statements)

References 18 publications

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“…So, fault-tolerance must be taken into consideration within the very fabrication process to obtain reasonable production yields [1,10]. These ideas are already quite old, see [43] for an early treatment of the topic, but have continued to persist into the most recent developments in VLSI technology.…”

Section: Previous Workmentioning

confidence: 99%

An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover

Fernau

Niedermeier

2001

Journal of Algorithms

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Section: Previous Workmentioning

confidence: 99%

An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover

Fernau

Niedermeier

2001

Journal of Algorithms

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“…One approach consists in introducing physical or time redundancy [1], [6]. In physical redundancy, the same computation is performed by different processing elements, while in time redundancy it is performed at different times by the same elements; the results are then compared to check for error occurrence.…”

Section: Introductionmentioning

confidence: 99%

“…Another approach uses coding teclmiques [ 1 ], [5 ], [ 12], where the input data is represented by a suitable code and computation is peffonned on the modified data. The results are then checked; whenever the output does not belong to lhat code, an error has occurred and a fault has been detected.…”

Section: Introductionmentioning

confidence: 99%

Concurrent error detection in fast FNT networks

Tahir

Dlay

Naguib

et al. 1994

Dependable Computing — EDCC-1

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For many real-time and scientific applications, it is desirable to perform signal and image processing algorittuns by means of special hardware in very high speed. With the advent of VLSI technology, large collections of processing elelnents can be used to achieve high-speed computations. In such designs, some level of fault tolerance must be obtained to ensure the validity of the results. Fennat number transfonns (FNT's) are attractive for file implementation of digital convolution because the computations are carried out in modular afittunetic which offer three advantages: no round-off error, no multiplications in the transform, and decomposition into fast algorithm analogous to the FFT. In this paper we present a fault-detectable array architecture for the fast implementation of Fernlat number transform. The results show that the design offers concu trent error detection (CED) using very low hardware and time overheads.

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“…Reliability is often a critical issue in applications of high-performance systolic or wavefront array processors, and for that reason much recent work has addressed the problems of on-line error detection (see, for example, [1]). We consider in this paper a flexible and general methodology for incorporating error detection in array design.…”

Section: Introductionmentioning

confidence: 99%

“…For example [1] describes algorithm-based techniques that are especially suited to systolic arrays, but these are applicable only to a subset of linear systems, and it is unclear how to use *This work was supported in part by NSF Grant MIP-8912100, and U.S. Army Research Office-Durham Grant DAAL03-89-K-0074. them on problems like the substring comparison we consider in Section 2.…”

Section: Introductionmentioning

confidence: 99%

Error detection in arrays via dependency graphs

Sha

Steiglitz

1992

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. This paper describes a methodology based on dependency graphs for doing concurrent run-time error detection in systolic arrays and wavefront processors. It combines the projection method of deriving systolic arrays from dependency graphs with the idea of input-triggered testing. We call the method ITRED, for Input-driven 7~me-Redundancy Error Detection. Tests are triggered by inserting special symbols in the input, and so the approach gives the user flexibility in trading off throughput for error coverage. Correctness of timing is proved at the dependency graph level. The method requires no extra PEs and little extra hardware. We propose several variations of the general approach and derive corresponding constraints on the modified dependency graphs that guarantee correctness. One variation performs run-time error correction using majority voting. Examples are given, including a dynamic programming algorithm, convolution, and matrix multiplication.

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Fault Tolerance Techniques for Systolic Arrays

Cited by 88 publications

References 18 publications

An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover

An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover

Concurrent error detection in fast FNT networks

Error detection in arrays via dependency graphs

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