Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density

IEEE Trans. Nanotechnology

Leblebici

2009

Self Cite

This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A faulttolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10 −5 ). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.Index Terms-Fault-tolerant architecture, high defect density, redundancy, reliability of nanoelectronic systems.1536-125X/$25.00

Section: Analytical Approach For Statistical Analysis Of Fault-tsupporting

confidence: 52%

“…In this paper, pdfs are constructed using an MC simulator described in [25] and [27] to acquire conditional output values on a large sample of different fault patterns. An extended transistorlevel fault model that implements 16 possible defects is used [25], [27].…”

Section: Analytical Approach For Statistical Analysis Of Fault-tmentioning

confidence: 99%

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Stanisavljević

IEEE Trans. Nanotechnology

Leblebici

2009

Self Cite

“…The differential circuit presented in Fig. 2 (b) carries out a weighted average and dynamic compression of the output voltage, [20]. The digital inputs may be incorrect or sustain a large amount of voltage variation.…”

Section: Circuit-level Realizationsmentioning

confidence: 99%

Neuromorphic microelectronics from devices to hardware systems and applications

2016

NOLTA

Neuromorphic systems aiming at mimicking some characteristics of the nervous systems of living humans or animals have been developed since the late 1980s', taking benefit of intrinsic properties and increasing performances of the successive silicon fabrication technologies. A regain of interest has been observed in the middle of the 2010s', which manifests itself from the emergence of large-scale projects integrating various computational and hardware perspectives, by the increased interest and involvement of industry and the growth of the volume of scientific publications. This paper reviews research directions and methods of neuromorphic microelectronics hardware, the developed hardware and its performance, and discusses current issues and potential future developments.

“…Moreover, the analysis of reliability of different circuits has been undertaken starting from the simple NOR Boolean gate as depicted in Figure 2, where Monte Carlo (SPICE) analysis have been applied using the developed tool ( [4], [5]). Two implementations of the circuits have been selected, and comparatively analyzed.…”

Section: Previous Workmentioning

confidence: 99%

“…an maximal input range of 30% of probability of failure for each transistor is already a significant value. More complex circuits have been analyzed [5]. Finally, an analysis of the optimal granularity of the redundant blocks is presented in [5].…”

Section: Previous Workmentioning

confidence: 99%

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

Stanisavljević

Gürkaynak

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

et al. 2007

This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. Characteristics of the averaging/thresholding layer are emphasized. A complete tool based on Monte Carlo simulation for a-priori functional fault tolerance analysis was used for analysis of distinctive cases and topologies. A full chip CMOS integrated design of the 128-bit AES cryptography algorithm with multiple cores that incorporate reliability architectures is shown. Categories and Subject Descriptors General termsReliability. KeywordsFault-tolerant architecture, high defect density, reliability of submicron and nanoelectronic systems.