Fault-Tolerance in Nanocomputers: A Cellular Array Approach

Abstract

Asynchronous cellular arrays have gained attention as promising architectures for nanocomputers, because of their lack of a clock, which facilitates low power designs, and their regular structure, which potentially allows manufacturing techniques based on molecular self-organization. With the increase in integration density comes a decrease in the reliability of the components from which computers are built, and implementations based on cellular arrays are no exception to this. This paper advances asynchronous cellular arrays that are tolerant to transient errors in up to one third of the information stored by its cells. The cellular arrays require six rules to describe the interactions between the cells, implying less complexity of the cells as compared to a previously proposed (nonfault-tolerant) asynchronous cellular array that employs nine rules.

High-Threshold Low-Overhead Fault-Tolerant Classical Computation and the Replacement of Measurements with Unitary Quantum Gates

“…If gates are allowed to interact with any given gate in the code, we must allow for wires which can carry a signal farther than the typical "nearest neighbors" interaction, and any wire must be expected to have a signal degradation which is exponential in its length [2,11]. Another impracticality is that the code size required for these random constructions, as well as explicit constructions based on randomization, has been estimated to be large [1][2][3]14].…”

“…This is due to an apparent need for high redundancy (number of fundamental components required to construct a noise-free logical gate), the need to continually connect and reconnect bits "at random" at a potentially large spatial separation, and the difficulty of both analytically calculating the performance for moderate code sizes and simulating the performance in the low-error regimes required for reliable computation [1][2][3][4][5][6][7][8][9]. The field of probabilistic cellular automata was partially motivated by addressing the second problem, but has not to-date produced a complete and feasible FTCC scheme [10][11][12][13][14][15][16][17][18][19][20][21]. A second method for FTCC was developed more recently in the context of quantum computing, and involves "concatenating" errorcorrection codes and logic gates .…”

The End of Moore’s Law: Opportunities for Natural Computing?

“…Synchronous updating requires the distribution of a clock, as well as sufficient memory in each cell to store its current state as well as its next state. An alternative, asynchronous, timing model has been explored in [49,50] that allows cells to operate more independently from each other, thus emphasizing the locality of their interactions. In an asynchronous CA, each cell may undergo a transition with a certain probability, but only so if the cell's state and the states of its neighbors match the left-hand side of a transition rule.…”

Desigining Circuits from Imperfect Components in VISI Giga-scale Technologies

“…These techniques are well suited for transmission mediums, but their implementation for computing circuits is not straightforward. One of the main difficulties is that codification requires circuits to code/encode information, if these functions are not fault free the whole system tolerance is Since considering nanotechnology for electronic design all fault and defect tolerant techniques have been revisited to provide architectural solutions for nanocomputing [15,[25][26][27] . All these techniques, although different, are based on the same principle: redundancy.…”