Fault Secure Encoder and Decoder Designs for Matrix Codes

Liu, Shanshan; Xiao, Liyi; Guo, Jifeng; Mao, Zhigang

doi:10.1109/cadgraphics.2015.12

Cited by 2 publications

(1 citation statement)

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“…Therefore, a number of techniques have been proposed to protect the encoders, for example of SEC [11] and SEC-DAEC [12] codes. Concurrent error detection has also been considered for Orthogonal Latin Square Codes [13], [14] or Matrix codes [15]. However, all those solutions are specifically designed for a type of codes and not generally applicable.…”

Section: Introductionmentioning

confidence: 99%

Correction Masking: A Technique to Implement Efficient SET Tolerant Error Correction Decoders

Liu

Reviriego

Argyrides

et al. 2022

IEEE Trans. Device Mater. Relib.

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Single Event Transients (SETs) can be a major concern for combinational circuits. Its importance grows as technology scales because a small charge can create a large disturbance on a circuit node. One example of circuits that can suffer from SETs is the decoders of the Error Correction Codes (ECCs) that are used to protect memories from errors. This paper presents Correction Masking (CM), a technique to implement SET tolerant syndrome decoders. The proposed technique is presented and evaluated both in terms of protection effectiveness and circuit overhead. The results show that it can provide an effective protection while reducing the circuit area and power significantly compared to a Triple Modular Redundancy (TMR) protection. An interesting result is that Correction Masking also reduces the delay as it adds less logic in the critical path than TMR. Finally, the proposed technique can be used for any syndrome decoder. This means that it is applicable to many of the ECCs used to protect memories such as Single Error Correction (SEC), Single Error Correction Double Error Detection (SEC-DED), Single Error Correction Double Adjacent Error Correction (SEC-DAEC), and 3-bit burst codes.

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