Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders

Abstract

Abstract-In this paper, a methodology for the development of fault-tolerant adders based on the Radix 2 Signed Digit (SD) representation is presented. The use of a number representation characterized by a carry propagation confined to neighbor digits implies interesting advantages in terms of error detection, fault localization, and repair. Errors caused by faults belonging to a considered stuck-at fault set can be detected by a parity-based technique. In fact, a carry-free adder preserving the parity of the augends can be implemented allowing fault detection by using a parity checker. Regarding fault localization, the "carry-free" property of the adder ensures the confinement of the error due to a permanent fault to only few digits. The detection of the faulty digit has been obtained by using a recomputation with shifted operands method. Finally, after the fault localization, graceful degradation of the system intended as the reduction of the performances versus a correct output computation can be obtained by using two different procedures. The first one allows obtaining the correct output by recomputing the result performing two different shift operations and using the intersection of the obtained results to recover the correct output, while the second one is based on a reduced dynamic range approach, which allows us to obtain the result in only one step, but with fewer output digits.

A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis

“…Noting that the possible values for Φ are Φ = w 2 = {10} 2 and Φ = w = {01} 2 , one can find the corresponding possible (η h + η l ) 2 using (12) and (13). This is achieved by putting both inputs in (12) or (13) as η h + η l .…”

“…The result of this comparison is the error indication flag of the corresponding block. This method has been utilized in the literature to develop a fault detection scheme for different applications, see for example [3], [13], [14], [15].…”

Localization of Faults in Radix-n Signed Digit Adders

“…The most widely applied techniques to obtain error correction in adder circuits are based on time-redundancy [1], or on the residue number system representation [2], [3]. In [4], [5] we propose a parity check scheme for radix-2 SD adders that allows the fault localization and the graceful degradation of the faulty adder. Instead, our solution proposed in [6] is based on generic r-radix signed digit representation and the correctness of the adder operation is checked using a residue of the input operands.…”

“…The goal of this paper is to extend the work presented in [6] discussing the localization of a faulty resource in a SD adder and to propose a graceful degradation approach to reconfigure the SD adder using the remaining fault free resources. We remark that differently from [4], [5] the method proposed in this paper is suitable for a generic r radix SD representation and both the fault localization and the graceful degradation approach can be achieved with less complexity than the algorithm proposed in [4], [5]. The paper is organized as follows: in section II a background of r-radix SD arithmetic is given and the error detection method is presented for the adder operation.…”

“…Section III provides a discussion of the different cases of fault localization and shows the related algorithm. The proposed graceful degradation approach is presented and a comparison of this method with the procedure proposed in [4], [5] is provided. Finally, in Section IV, the conclusions are drawn.…”