Fault equivalence identification using redundancy information and static and dynamic extraction

Amyeen, M. Enamul; Fuchs, W.K.; Pomeranz, Irith; Boppana, Vamsi

doi:10.1109/vts.2001.923428

Cited by 23 publications

(35 citation statements)

References 16 publications

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“…Dominators are widely used in several areas, such as code optimization in compilers [20] and test pattern generation techniques [21]. Recently, dominators have been used in logic synthesis for non-disjoint decomposition of Boolean functions [19].…”

Section: Preliminariesmentioning

confidence: 99%

Dominator-based partitioning for delay optimization

Bañeres

Cortadella

Kishinevsky

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techniques are not always suitable for delay and area logic optimizations. The paper presents an approach that uses a dominator-based partitioning and conventional logic synthesis techniques for delay optimization of large networks. The calculation of dominators is crucial to find topologically ordered clusters suitable for logic restructuring. As a result, a scalable and efficient strategy for delay optimization is proposed and evaluated, showing tangible improvements with respect to existing techniques. A comparison with a standard mincut-based partitioning technique is also presented.

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Section: Preliminariesmentioning

confidence: 99%

Dominator-based partitioning for delay optimization

Bañeres

Cortadella

Kishinevsky

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

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“…These methods are fast but they have pessimistic results since they operate on fan-out free circuit regions only. Functional fault equivalence methods are more expensive but they typically identify more classes [1,2,7,9,12]. Some of these methods [1,2,12] use logic implications and/or dominator information to prove equivalence.…”

Section: Introductionmentioning

confidence: 99%

“…Functional fault equivalence methods are more expensive but they typically identify more classes [1,2,7,9,12]. Some of these methods [1,2,12] use logic implications and/or dominator information to prove equivalence. Since identifying logic implications is NP-hard [11], these methods do not utilize the complete set of logic implications and they may not return the complete set of fault equivalence classes.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Veneris

Chang

Abadir³

et al. 2005

J Electron Test

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Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. The advantage of the approach lies in its practicality since it uses conventional ATPG and it automatically benefits from advances in the field. Experiments on ISCAS'85 and full-scan ISCAS'89 circuits demonstrate the competitiveness of the method and measure the performance of simulation for fault equivalence.

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“…By adopting heuristic techniques as shown in [8] [9], equivalent fault pairs can be quickly identified by bounding the search space. However, when the number of fault pairs to be targeted is large, either identifying all the equivalent faults using a deterministic or a heuristic method can take a very long time.…”

Section: Complexitymentioning

confidence: 99%

Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation

Amyeen²,

Venkataraman³

et al.

Proceedings. 21st VLSI Test Symposium, 2003.

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Effective generation of diagnostic vectors can be assisted by a fast diagnostic fault simulator and an equivalence identification tool. Diagnostic fault simulation can be an expensive process for large circuits. If a large number of fault pairs are passed to an equivalence identification tool, it would take a long time. In this paper, a novel approach is proposed to concurrently execute diagnostic fault simulation and equivalence identification during diagnostic test generation, thereby reducing the overall execution time. Experimental results on industrial circuits and benchmark circuits demonstrate the potential of the proposed method.

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Fault equivalence identification using redundancy information and static and dynamic extraction

Cited by 23 publications

References 16 publications

Dominator-based partitioning for delay optimization

Dominator-based partitioning for delay optimization

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG

Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation

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