Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective

Löfwenmark, Andreas; Nadjm‐Tehrani, Simin

doi:10.1016/j.sysarc.2018.04.001

Cited by 18 publications

(5 citation statements)

References 16 publications

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“…So, the combination of hardware and software techniques combined at different abstraction levels are usually required to detect complex hardware faults such as MBU and transient faults, as supported hardware techniques alone might not be sufficient [34,39,56,48,36]. However, cross-requirements research contributions that aim at reconciling reliability, DC and time predictability are still scarce (e.g., [57,58]).…”

Section: Discussionmentioning

confidence: 99%

“…Measurement-based (deterministic) timing analysis has been object of significant attention with the development of multiple methods applied to specific safety regulations and domains such as automotive [69], avionics [58] and industrial control [55] domains. It is also a common industrial practice.…”

Section: Temporal Independencementioning

confidence: 99%

“…Agrawal et al [177] provide a specific solution to manage memory bandwidth dynamically on COTS multi-core devices while still preserving a sufficient degree of time predictability. The impact of fault-tolerance mechanisms on time predictability for multi-core devices has also received some attention [58] since this aspect is too often overlooked. Finally, some authors consider the use of probabilistic timing analysis as a way of relieving end users from the cumbersome task of mastering execution time variability in complex multi-core devices [64,178,179].…”

Section: Avionics Domainmentioning

confidence: 99%

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Multi-core Devices for Safety-critical Systems

et al. 2020

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Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Section: Discussionmentioning

confidence: 99%

Section: Temporal Independencementioning

confidence: 99%

Section: Avionics Domainmentioning

confidence: 99%

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Multi-core Devices for Safety-critical Systems

et al. 2020

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“…Finally, Löfwenmark and Nadjm-Tehrani [67] published a survey that regrouped works focusing on multicore systems in avionics. They suggested that there is an increased sensitivity to faults due to shrinking transistor sizes, and highlighted areas where research is still needed.…”

Section: Soc Monitoring and Diagnosismentioning

confidence: 99%

Incremental Modeling and Monitoring of Embedded CPU-GPU Chips

Djedidi

Djeziri

2020

Processes

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This paper presents a monitoring framework to detect drifts and faults in the behavior of the central processing unit (CPU)-graphics processing unit (GPU) chips powering them. To construct the framework, an incremental model and a fault detection and isolation (FDI) algorithm are hereby proposed. The reference model is composed of a set of interconnected exchangeable subsystems that allows it to be adapted to changes in the structure of the system or operating modes, by replacing or extending its components. It estimates a set of variables characterizing the operating state of the chip from only two global inputs. Then, through analytical redundancy, the estimated variables are compared to the output of the system in the FDI module, which generates alarms in the presence of faults or drifts in the system. Furthermore, the interconnected nature of the model allows for the direct localization and isolation of any detected abnormalities. The implementation of the proposed framework requires no additional instrumentation as the used variables are measured by the system. Finally, we use multiple experimental setups for the validation of our approach and also proving that it can be applied to most of the existing embedded systems.

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“…These have to be reduced as much as possible so that critical systems can perform correctly in the required period of time. Many different approaches have appeared in order to tackle this issue [16], where we can point out task scheduling [13], cache partitioning [27], timing analysis [15] or task and memory mapping [6]. These different approaches are generally synergistic and can be implemented together.…”

Section: Introductionmentioning

confidence: 99%

Heterogeneous multicore SDRAM interference analysis

Gonzalez

Boniol

Bouchebaba

et al. 2021

29th International Conference on Real-Time Networks and Systems

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The purpose of this paper is to describe a set of DDR3 SDRAM interference estimation cost functions. The arbitration system of the SDRAM controller heavily impact the interference analysis. In this work, three arbitration are considered, corresponding to the situations where the accessed memory address belongs to the same block address, different memory banks and different rows. The aim of these functions is to estimate the instructions interference overhead may suffer when concurrently accessing these three logical addresses in a SDRAM saturation context. To develop these interference expressions, specific measurement systems, microbenchmarks and theory on SDRAM controllers have been used. CCS CONCEPTS• Computer systems organization → Real-time system architecture; Real-time system specification; Real-time system architecture.

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Fault and timing analysis in critical multi-core systems: A survey with an avionics perspective

Cited by 18 publications

References 16 publications

Multi-core Devices for Safety-critical Systems

Multi-core Devices for Safety-critical Systems

Incremental Modeling and Monitoring of Embedded CPU-GPU Chips

Heterogeneous multicore SDRAM interference analysis

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