FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

Pnevmatikatos, Dionisios; Becker, Tobias; Brokalakis, Andreas; Bruneel, Karel; Gaydadjiev, Georgi; Luk, Wayne; Papadimitriou, Kyprianos; Papaefstathiou, Ioannis; Pell, Oliver; Pilato, Christian; Robart, M.; Santambrogio, Marco D.; Sciuto, D.; Stroobandt, Dirk; Todman, Tim

doi:10.1109/dsd.2012.59

Cited by 6 publications

(2 citation statements)

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“…We expect this to be a collection of kernels with different optimization techniques (effectively, different versions of multiple kernels to be benchmarked and profiled) and an application driver, which will implement the DAG structure. One important challenge here is to isolate the driver from the application itself, preferably in the form of a rudimentary run-time system that will build on the FASTER runtime system [15]. While this solution seems theoretically feasible, the technical challenges cannot be ignored.…”

Section: ) the Input Data (1)mentioning

confidence: 99%

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

Stroobandt

Vărbănescu²,

Ciobanu³

et al. 2016

2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-To handle the stringent performance requirements of future exascale-class applications, High Performance Computing (HPC) systems need ultra-efficient heterogeneous compute nodes. To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time.In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on. EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques. Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field.

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Section: ) the Input Data (1)mentioning

confidence: 99%

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

Stroobandt

Vărbănescu²,

Ciobanu³

et al. 2016

2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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“…The basic components of the RTSM model we adopted in the FASTER project were presented in [13]. The RTSM would incorporate operating-system style services that will allow high level operations on the hardware circuits.…”

Section: Run-time System Managermentioning

confidence: 99%

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration

Papadimitriou

Pilato

Pnevmatikatos

et al. 2012

2012 IEEE 15th International Conference on Computational Science and Engineering

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Abstract-During the last few years, there is an increasing interest in mixing software and hardware to serve efficiently different applications. This is due to the heterogeneity characterizing the tasks of an application which require the presence of resources from both worlds, software and hardware. Controlling effectively these resources through an integrated tool flow is a challenging problem and towards this direction only a few efforts exist. In fact, a framework that seamlessly exploits both resources of a platform for executing efficiently an application has not yet come into existence. Moreover, reconfigurable computing often incorporated in such platforms due to its high flexibility and customization, has not yet taken off due to the lack of exploiting its full capabilities. Thus, the capability of reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) to be dynamically reconfigured, i.e. reprogramming part of the chip while other parts of the same chip remain functional, has not yet taken off even in small-scale basis. The inherent difficulty in using the tools to control this technology has kept it back from being adopted by academia and industry alike.The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a design methodology and a tool flow that will enable designers to implement effectively and easily a system specification on a platform combining software and reconfigurable resources. The FASTER framework accepts as input a high-level description of the application and the architectural details of the target platform, and through certain steps it can enable the full use of the capabilities of the platform, while at the same time it should be flexible enough so as to balance efficiently performance, power and area. One of the main novelties is the incorporation of partial reconfiguration as an explicit design concept at an early stage of the design flow. We target different applications from the embedded, desktop and high-performance computing domains. In all cases we will demonstrate the effectiveness of the proposed framework in exploiting the inherent parallelism of applications and enabling the runtime adaptation of the platforms to the changing needs of the applications.

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