Fast transient response enhancement circuit for LDO

Guo, Zhongjie; Gong, Chengjun; Bai, Ruokai

doi:10.1109/icicm59499.2023.10365762

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2024

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“…To provide good isolation between the SWPC noisy output and the very noise-sensitive RF and/or highperformance analog blocks, the PSR of LDO is becoming a very demanding specification [4,5]. Besides PSR, transient response is one of the most important specifications for LDOs [6].…”

Section: Introductionmentioning

confidence: 99%

A fast-transient dual loop LDO with high PSR

Fang,

Jin,

Liu

et al. 2024

IEICE Electron. Express

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In this work, the design of a 0.18μm CMOS dual loop capacitor-less low-dropout regulator (LDO) to achieve fast-transient response and good power supple rejection (PSR) is proposed for system-on-chip (SoC) power supply. The proposed LDO has a high slew-rate fast loop for enhancing transient response capability, and the high gain slow loop to improve PSR. Results show that the LDO consumes 100μA quiescent current, delivering a 50mA load current over a 30pF load. The maximum transient output-voltage variation is within 10% of the output voltage with recovery time of less than 81ns with a load step between 500μA and 50mA with 50ns edge times. The PSR is better than 50dB at 1MHz.

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Section: Introductionmentioning

confidence: 99%