Fast‐transient high‐performance 0.18 μm CMOS LDO for battery‐powered systems

Pérez-Bailón, J.; Márquez, A.; Calvo, B.; Medrano, N.; Martínez, P.A.

doi:10.1049/el.2016.4541

Cited by 14 publications

(10 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Introducing substitution terms given in (22) and integrating both sides of (21) yields the definite integral expressed in (23). Finally, evaluating the integral in the given interval and dividing it by e CA ⋅ t + CB ⋅ t 2 yields v out t expression given in (24). Back substituting the terms in (22) leads to (10) d e (1/V EQ ⋅ C) I RO ⋅ t + sign(Δi load ) ⋅ I PMOS ⋅ f clk ⋅ (t 2 /2) ⋅ v out t dt = e (1/V EQ ⋅ C) I RO ⋅ t + sign(Δi load ) ⋅ I PMOS ⋅ f clk ⋅ (t 2 /2) ⋅ i in t − i load (t) C…”

Section: Appendixmentioning

confidence: 99%

“…Complimentary to these techniques, this work develops models for estimating digital LDO transient behaviours, such as ripple magnitudes after load current or voltage reference changes. Recently, various techniques to enhance LDO transient response, such as using dual control loops in [22], dynamic biasing in [24], or event‐driving logic in [25], have been reported. Such enhance techniques can be included LDO modelling as shown in [22, 25].…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Digital LDO modelling techniques for performance estimation at early design stage

Leitner

Wang

2018

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated.

show abstract

Section: Appendixmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Digital LDO modelling techniques for performance estimation at early design stage

Leitner

Wang

2018

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…But this requires extra external pins and cannot be integrated into the whole chip. To remove external components and reduce system size, capacitorless LDOs are proposed in [2][3][4][5][6][7]. But all previous LDOs have trade-offs between wide input and load current ranges, the need for large off-chip capacitors, and output transient response.…”

Section: Introductionmentioning

confidence: 99%

A wide input range, external capacitor-less LDO with fast transient response

Gao

Cai

Yan

et al. 2022

Preprint

View full text Add to dashboard Cite

A high-voltage, external capacitor-less low-dropout regulator (HVLDO) with a transient enhancement loop is presented in this work. The proposed HVLDO is designed with high withstand voltage LDMOS transistors and a transient enhancement loop is proposed to properly inject or sink current to/from the gate and output nodes of the power transistors to achieve fast transient response under wide load range conditions and high stability. This HVLDO is fabricated in 0.5 μm SOI BCD process with an active area of 0.29 mm2. It operates over an input voltage range of 5.2 to 20 V, provides an output voltage of 5 V and a maximum load of 100 mA, while supporting load capacitances from 0 pF to 1 μF. Measurements show that this design has a line regulation of 0.88 mV/V and a load regulation of 0.22 mV/mA. The proposed HVLDO features fast line transient response of 60/20 mV@9.8 V/µs, fast load transient response of 30/70 mV@100 mA/µs, and recovery time of 2 µs without external capacitors. Compared with the prior art, this work achieves the best transient FOM of 12.19 fs.

show abstract

“…A low-dropout (LDO) regulator that supplies low noise, ripple-free supply voltages to many different blocks is one of the core circuits of the power management system. LDOs require the elimination of external capacitors to increase density and reduce quiescent current to prolong the battery cycle [1][2][3][4][5][6][7][8][9]. However, an external capacitorless LDO with a low quiescent current has a problem that the undershoot/overshoot voltage is increased for sudden load variation and the load transient response performance is degraded [3,[10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Fast transient low‐dropout regulator with undershoot and settling time reduction technique

Lee

Kwon

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.

show abstract

Fast‐transient high‐performance 0.18 μm CMOS LDO for battery‐powered systems

Cited by 14 publications

References 7 publications

Digital LDO modelling techniques for performance estimation at early design stage

Digital LDO modelling techniques for performance estimation at early design stage

A wide input range, external capacitor-less LDO with fast transient response

Fast transient low‐dropout regulator with undershoot and settling time reduction technique

Contact Info

Product

Resources

About