Fast SystemC Processor Models with Unicorn

Jünger, Lukas; Weinstock, Jan Henrik; Leupers, Rainer; Ascheid, Gerd

doi:10.1145/3300189.3300191

Cited by 7 publications

(2 citation statements)

References 2 publications

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“…SystemC additionally lets in his customers to paintings at a better stage of abstraction for permitting extraordinarily quicker and extra effective architectural tradeoff evaluation of their layout. There are 5 essential software program extensions furnished via way of means of SystemC to version the device hardware [23]…”

Section: System Cmentioning

confidence: 99%

Smart System Modeling and Simulation design of Hemodialysis Machine by SysML with SystemC-AMS

Abdulhameed¹,

AlKindy²,

Al-Mahdawi³

2022

J Eng App Sci Technol

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The corrections of the large and complex systems have become an issue of great importance recently due to the system development process. The device technology is quite complex and encompasses various disciplines of engineering, medicine, biology, and critical patient-machine interfaces. In this paper, we proposed a simulation approach to the verification and validation of the system of the hemodialysis machine (HD machine) specified by the SysML language. The simulation is carried out through intelligent translation based on the specifications of SysML into SystemC-AMS models. To evaluate and validate the system design, they are translated into a set of formulas and requirements verified when run on the available tools, COSE DA technologies, the WSN simulator developed by SystemC-AMS.

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Section: System Cmentioning

confidence: 99%

Smart System Modeling and Simulation design of Hemodialysis Machine by SysML with SystemC-AMS

Abdulhameed¹,

AlKindy²,

Al-Mahdawi³

2022

J Eng App Sci Technol

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“…Nonetheless, it offers fewer features than QEMU, and it has been ported to only a few hardware platforms. Its use is limited to research purposes [29].…”

Section: Background and Proposal Description 21 Hardware/software Cmentioning

confidence: 99%

Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms

et al. 2021

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Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq−7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.

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