Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

Meyer, J.; Noguera, Juanjo; Hübner, Michael; Braun, Lars; Sander, Oliver; Gil, Raúl Mateos; Stewart, Rodney Anthony; Becker, Juergen

doi:10.1109/date.2011.5763244

Cited by 10 publications

(3 citation statements)

References 3 publications

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“…Figure 11 illustrates our design flow on the left side, while the right side of the figure illustrates how our repository may be utilized by user applications at runtime. Though our repository lends itself to dynamic reconfiguration and a runtime system [Meyer et al 2011;Cazzaniga et al 2012], this is not within the scope of our work. The large number of precompiled DSEs ensures sufficient coverage of the design space.…”

Section: Design Flowmentioning

confidence: 95%

River

Brugger

Hillenbrand

Balzer

2014

ACM Trans. Reconfigurable Technol. Syst.

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For high-performance embedded hard-real-time systems, ASICs and FPGAs hold advantages over generalpurpose processors and graphics accelerators (GPUs). However, developing signal processing architectures from scratch requires significant resources. Our design methodology is based on sets of configurable building blocks that provide storage, dataflow, computation, and control. Based on our building blocks, we generate hundreds of thousands of our dynamic streaming engine processors that we call DSEs. We store our DSEs in a repository that can be queried for (online) design space exploration. From this repository, DSEs can be downloaded and instantiated within milliseconds on FPGAs. If a loss of flexibility can be tolerated then ASIC implementations are feasible as well. In this article we focus on FPGA implementations. Our DSEs vary in cores, computational lanes, bitwidths, power consumption, and frequency. To the best of our knowledge we are the first to propose online design space exploration based on repositories of precompiled cores that are assembled of common building blocks. For demonstration purposes we map algorithms for image processing and financial mathematics to DSEs and compare the performance to existing highly optimized signal and graphics accelerators. ACM Reference Format:Christian Brugger, Dominic Hillenbrand, and Matthias Balzer. 2014. RIVER: Reconfigurable flow and fabric for real-time signal processing on FPGAs.

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Section: Design Flowmentioning

confidence: 95%

River

Brugger

Hillenbrand

Balzer

2014

ACM Trans. Reconfigurable Technol. Syst.

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“…Therefore, this initial system should only contain the hardware components which are absolutely necessary to run an embedded processor subsystem (i.e., meet the start-up deadline). Detailed explanation of the low-level FPGA implementation techniques are given in [15].…”

Section: A Reducing Fpga Configuration Timementioning

confidence: 99%

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs

Meyer

Noguera

Huebner

et al. 2011

2011 21st International Conference on Field Programmable Logic and Applications

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In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the startup time of the embedded software. Thereby the start-up time for timing-critical parts of a design neither dependent on the complexity nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.

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“…A partitioning approach for the implementation of a sequential DAB receiver on a Virtex platform has been presented in [4]. Different methods for using DPR together with the low-cost Xilinx Spartan-6 platform have been published in [5] and [6].…”

Section: Prior Artmentioning

confidence: 99%

Real-time signal processing on low-cost-FPGAs using dynamic partial reconfiguration

Feilen

Ihmig

Zahlheimer

et al. 2011

2011 International Symposium on Integrated Circuits

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The limited number of logic elements makes the implementation of signal processing chains on low-cost FPGAs a challenging task. In order to allow the implementation of complex designs on devices with limited resources, we propose the subpartitioning of a processing chain into several modules, which are loaded and executed in a round-robin fashion using dynamic partial reconfiguration (DPR) of FPGAs. The DPR architecture requires input data pre-buffering which introduces delay. These circumstances are first considered in a theoretical analysis and later applied to a broadcast receiver chain, where the benefits and drawbacks of the architecture are highlighted.

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Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

Cited by 10 publications

References 3 publications

River

River

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs

Real-time signal processing on low-cost-FPGAs using dynamic partial reconfiguration

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