2019
DOI: 10.1109/tps.2019.2928535
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Fast SiC Switching Limits for Pulsed Power Applications

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Cited by 12 publications
(5 citation statements)
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“…The gate drive circuit requires careful consideration of various external switching factors, including parasitic elements, circuit components, and PCB layout [128]. Traditional commercial gate drivers, often using push-pull or totem-pole driving topologies, are not suitable for high-current switching with rise times on the order of 10-20 ns [129]. Moreover, when multiple switches are connected in series or parallel, the switching synchronization is also important.…”
Section: Challenges and Trends A Device Developmentmentioning
confidence: 99%
“…The gate drive circuit requires careful consideration of various external switching factors, including parasitic elements, circuit components, and PCB layout [128]. Traditional commercial gate drivers, often using push-pull or totem-pole driving topologies, are not suitable for high-current switching with rise times on the order of 10-20 ns [129]. Moreover, when multiple switches are connected in series or parallel, the switching synchronization is also important.…”
Section: Challenges and Trends A Device Developmentmentioning
confidence: 99%
“…In the framework of ADRC, combined with the control structure of Figure 6, Equations ( 4) and ( 6) can be reformulated to obtain (7):…”
Section: Formation Of Adrc-based Current Controllermentioning
confidence: 99%
“…[5] designed a pulse power supply system with a special structure to develop the technology required for inertial fusion power plants. In addition, the emergence of new silicon carbide devices has improved the application range and performance of pulse power supplies [6][7][8][9][10]. Therefore, pulse power supply technology is in possession of great potential for development.…”
Section: Introductionmentioning
confidence: 99%
“…Using accurate models of the SiC MOSFET, an initial design for the driver can be accomplished [29,44]. The external parasitic inductances of the tracks (typically around 20 nH) should also be considered for the design [45]. Another model including the inductances is presented in [29], while the power losses can also be modeled through analytical expressions [3].…”
Section: Parasitic Gate Loop Inductormentioning
confidence: 99%