Fast scan algorithms on graphics processors

Dotsenko, Yuri; Govindaraju, Naga K.; Sloan, Peter-Pike; Boyd, Clint; Manferdelli, John

doi:10.1145/1375527.1375559

Cited by 108 publications

(76 citation statements)

References 9 publications

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“…-There are a number of implementations of scan available in kernel languages [6,9,14,30]. These implementations encapsulate the barriers, fences, and multiple kernel invocations required in a correct and efficient implementation of scan and provide an interface through which the using programmer provides the ⊕ function.…”

Section: Proposed Methodologymentioning

confidence: 99%

Data Flow Algorithms for Processors with Vector Extensions

Barford

Bhattacharyya

Liu

2015

J Sign Process Syst

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Full use of the parallel computation capabilities of present and expected CPUs and GPUs requires use of vector extensions. Yet many actors in data flow systems for digital signal processing have internal state (or, equivalently, an edge that loops from the actor back to itself) that impose serial dependencies between actor invocations that make vectorizing across actor invocations impossible. Ideally, issues of inter-thread coordination required by serial data dependencies should be handled by code written by parallel programming experts that is separate from code specifying signal processing operations. The purpose of this paper is to present one approach for so doing in the case of actors that maintain state. We propose a methodology for using the parallel scan (also known as prefix sum) pattern to create algorithms for multiple simultaneous invocations of such an actor that results in vectorizable code. Two examples of applying this methodology are given: (1) infinite impulse response filters and (2) finite state machines. The correctness and performance of the resulting IIR filters and one class of FSMs are studied.

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Section: Proposed Methodologymentioning

confidence: 99%

Data Flow Algorithms for Processors with Vector Extensions

Barford

Bhattacharyya

Liu

2015

J Sign Process Syst

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“…The height W is the workload (i.e., the number of nonzero entries to be processed) of a thread. A tile is a basic work unit in matrix-based segmented sum method [20,35], which is used as a building block in our SpMV algorithm. Actually, the term "tile" is equivalent to the term "matrix" used in original description of the segmented scan algorithms [20,35].…”

Section: Data Decompositionmentioning

confidence: 99%

“…A tile is a basic work unit in matrix-based segmented sum method [20,35], which is used as a building block in our SpMV algorithm. Actually, the term "tile" is equivalent to the term "matrix" used in original description of the segmented scan algorithms [20,35]. Here we use "tile" to avoid confusion between a work unit of matrix shape and a sparse matrix in SpMV.…”

Section: Data Decompositionmentioning

confidence: 99%

“…Then we execute the matrix-based segmented sum (lines 32-33) on the tile. Because the segmented sum algorithm used here is very similar to the method described in [16], we refer the reader to [16] and several pervious GPU segmented sum algorithms [20,35] for details. But note that compared to [16], our method makes one difference: we store partial sums in a compact pattern (i.e., values are arranged in order from the first location in the thread work space), but not save them to locations of corresponding segment heads.…”

Section: Algorithm Descriptionmentioning

confidence: 99%

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Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

Liu

Vinter

2015

Parallel Computing

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Sparse matrix-vector multiplication (SpMV) is a central building block for scientific software and graph applications. Recently, heterogeneous processors composed of different types of cores attracted much attention because of their flexible core configuration and high energy efficiency. In this paper, we propose a compressed sparse row (CSR) format based SpMV algorithm utilizing both types of cores in a CPU-GPU heterogeneous processor. We first speculatively execute segmented sum operations on the GPU part of a heterogeneous processor and generate a possibly incorrect results. Then the CPU part of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement over the best existing CSR-based SpMV algorithms.

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“…This definition is also known as exclusive scan or prescan. Dotsenko et al [15] proposed a matrix-based algorithm for prefix scan on GPUs. Input data are partitioned into matrices with α rows and b columns and each matrix is processed by a multiprocessor.…”

Section: Prefix Scan Algorithmsmentioning

confidence: 99%

A Novel Computational Model for GPUs with Applications to Efficient Algorithms

Koike

Sadakane

2015

IJNC

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We propose a novel computational model for GPUs. Known parallel computational models such as the PRAM model are not appropriate for evaluating GPU-based algorithms. Our model, called AGPU, abstracts the essence of current GPU architectures such as global and shared memory, memory coalescing and bank conflicts. Using our model, we can evaluate asymptotic behavior of GPU algorithms more efficiently than the known models and we can develop algorithms that run fast on real GPU devices.As a showcase, we analyze the asymptotic behavior of basic existing algorithms including reduction, prefix scan, and comparison sorting. We further develop new algorithms by detecting and resolving performance bottlenecks of the existing algorithms. Our reduction algorithm has the optimal time and I/O complexities and works with non-commutative operators. Our comparison sorting algorithm has the optimal I/O complexity. Additionally, we show our algorithms run faster than the existing algorithms not only in theory but also in practice.

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Fast scan algorithms on graphics processors

Cited by 108 publications

References 9 publications

Data Flow Algorithms for Processors with Vector Extensions

Data Flow Algorithms for Processors with Vector Extensions

Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

A Novel Computational Model for GPUs with Applications to Efficient Algorithms

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