Fast recursive filtering with multiple slow processing elements

The requirements of high‐speed filtering are more serious in 2‐D digital filters than in 1‐D digital filters because the former must perform many more operations and deal with considerably more data. This paper proposes a systolic array implementation of 2‐D digital filters using 2‐D block processing. First, an extension of systolic array implementation for 1‐D block processing into 2‐D block processing is shown and then the circuit is decreased by improving it. This systolic array has a disadvantage in that the number of processing elements per sample increases in proportion to the processing speed. To improve this situation, we present an implementation method for obtaining the throughput proportional to the number of arrays by using multiple systolic arrays having multilayer structures. This circuit behaves like a 3‐D systolic array.

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High‐performance VLSI architecture suitable for control systems for state‐space digital filters using distributed arithmetic

Tsunekawa

Miura

1995

Electron Comm Jpn Pt III

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This paper proposes and evaluates high‐performance VLSI architecture for real‐time state‐space digital filters used in digital signal processing and digital control. A VLSI‐oriented highly parallel architecture for state‐space digital filters with high sampling rate and small latency has already been proposed by the authors. To speed up and reduce hardware complexity, the distributed arithmetic (of which processing time depends on only, word length) is applied to this architecture, making good use of highly accurate state‐space digital filters. The very high sampling rate can be implemented independently of filter order and the number of the input and output.

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Fast recursive filtering with multiple slow processing elements

Cited by 51 publications

References 26 publications

Fast direct implementations of two‐dimensional digital filters via systolic and wavefront arrays

Fast direct implementations of two‐dimensional digital filters via systolic and wavefront arrays

Systolic array implementation of 2‐D digital filters using 2‐D block processing

High‐performance VLSI architecture suitable for control systems for state‐space digital filters using distributed arithmetic

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