Fast prototyping of datapath-intensive architectures

Rabaey, Jan M.; Chu, Chi-min; Hoang, Phu; Potkonjak, Miodrag

doi:10.1109/54.82037

Cited by 256 publications

(127 citation statements)

References 10 publications

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“…8j 2 [0; T r 0 1]; p 2 PS t ; t 2 PROC g i1;i2 y tl i1 ;P i2 (15) g i1;i2 y tli2;P i1 (16) g i1;i2 g i1;i + y tl i ;P i2 0 18i 2 N1 (17) g i1;i2 g i1;i + y tli2;P i 0 18i 2 N1 (18) …”

Section: Ilp Model For Processor Allocation With Unfolding Factor Minunclassified

“…The objective of module selection is automatic allocation of each operation to a library of processors to synthesize a system using less silicon area and lower power. The module selection during scheduling has been addressed in [18]- [20] in the context of heuristic scheduling and in [14] for scheduling large-grain signal processing algorithms by ILP. In this paper we support fine-grain signal processing algorithms.…”

Section: Introductionmentioning

confidence: 99%

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Module Selection And Data Format Conversion For Cost-optimal Dsp Synthesis

Ito

Lucke

Parhi

IEEE/ACM International Conference on Computer-Aided Design

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“…8j 2 [0; T r 0 1]; p 2 PS t ; t 2 PROC g i1;i2 y tl i1 ;P i2 (15) g i1;i2 y tli2;P i1 (16) g i1;i2 g i1;i + y tl i ;P i2 0 18i 2 N1 (17) g i1;i2 g i1;i + y tli2;P i 0 18i 2 N1 (18) …”

Section: Ilp Model For Processor Allocation With Unfolding Factor Minunclassified

Section: Introductionmentioning

confidence: 99%

Module Selection And Data Format Conversion For Cost-optimal Dsp Synthesis

Ito

Lucke

Parhi

IEEE/ACM International Conference on Computer-Aided Design

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“…For example, the product y = 175 * x, can be computed in the following way: y = x <<7 + x << 5 + x << 4 + x << 3 + x. Since the shifts and additions are significantly more area, time, and power efficient, this transformations has been widely used in computer architecture, compilers [Mag88], and VLSI signal processing [Rab91].…”

Section: Implementation On Custom Datapath Asicsmentioning

confidence: 99%

Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach

Srivastava¹,

Potkonjak²

33rd Design Automation Conference Proceedings, 1996

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-Linear computations form an important type of computation that is widely used in DSP and communications. We introduce two approaches for power minimization in linear computations using transformations. First we show how unfolding combined with the procedure for maximally fast implementation of linear computations reduces power in single processor and multiprocessor implementations by factors 2.2 and 8 respectively. To accomplish this we exploit a newly identified property of unfolding whereby as a linear system is unfolded, the number of operations per sample at first decreases to reach a minimum and then begins to rise. For the custom ASIC implementation even higher improvements are achievable using the second transformational approach, which builds upon the unfolding based strategy of the first approach. We developed a method that combines the multiple constant multiplication (MCM) technique with the generalized Horner's scheme and unfolding in such a way that power is minimized. Throughput and Power in Linear SystemsLinear computations form an important type of computation that is widely used in video and image processing, DSP, control, communications, and many other applications. A large fraction of systems in these application domains are either linear, or have subsystems that are linear. This paper explores the relationship of throughput with increasingly important design metric -power. In particular, we seek to find the extent to which power consumption of linear systems can be reduced, both independently and in conjunction with throughput improvement, and to develop techniques for doing so.To explore the throughput and power relationship in linear systems we take a more thorough and systematic approach. First, we consider analytically as well as empirically the effect of several algorithm transformations that can be considered as the buildingblocks for exploring the power-throughput space. Specifically, we consider unfolding, which is the underlying transformation behind arbitrary throughput improvement, both separately and in combination with decomposition of multiplication-by-constants into primitive sequences of shifts and additions, factorization, common sub-expression elimination. Second, we consider implementations not just in the form of ASICs with applicationspecific datapaths as is usually the case, but also implementations based on single programmable processor and multiple programmable processors. This is important because increasingly programmable processors such as DSP-cores are the preferred medium of implementation as opposed to custom datapaths. Where does the Power Go, and How to Reduce It?In CMOS technology there are three sources of power consumption: switching current, short-circuit current, and leakage currents. The switching component not only dominates in most designs, but is also the only one which cannot be made negligible even when proper circuit design techniques are used. The average power consumption of a CMOS gate due to the switching component is given by:where is...

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“…3a). Under estimations, Hyper estimation for area, speed, and power is encapsulated [Rab91,Meh94], as well as property-based area estimation. A sample property-based estimation window is shown in Fig.…”

Section: Interface and Implementationmentioning

confidence: 99%

A methodology for guided behavioral-level optimization

Guerra¹,

Potkonjak²,

Rabaey³

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

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-Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive environment for guiding the exploration process. A prototype targeting behavioral-level optimization for datapath-intensive ASIC implementations has been developed. The key to the approach is encapsulated knowledge about the various optimizations and a set of techniques to automatically extract the "essence" of a design description. At each stage in the exploration process, the system suggests and ranks potential optimizations, both in terms of immediate and longer-term impact. It also provides evaluations of the design and of the likely affects each optimization will have on metrics like power and performance. In the new approach, the designer is responsible for making the actual optimization selections. However, using the provided guidance, designers can make decisions in a more informed manner, and therefore can explore the design solution space more effectively. The effectiveness of the approach is demonstrated on a number of designs. IntroductionTraditionally, concentration has been placed in the development of point tools and methodologies which address a single task within the optimization process. For example, in behavioral-level optimization, in addition to the approaches proposed for partitioning, template matching, and clock selection, there exist more than a hundred transformations [Bac94,Par95]. Some optimizations are restricted to optimization of a specific class of computation (e.g. only linear computations). Some focus on power optimization while others target area or throughput. Furthermore, some concentrate on reduction of just a specific sub-metric; for example, different power optimization techniques have been developed for reducing capacitance, for reducing activity, and for enabling voltage scaling.Effective global optimization, or optimization of a global objective function on current-day complex and heterogeneous applications, clearly requires the coordinated application of a collection of techniques. While many of the problems being addressed by the individual techniques are in themselves computationally intractable, an added layer of complexity clearly exists in deriving an entire optimization trajectory. This added complexity is due to the strong interdependency that exists between techniques. Exploring different trajectories is crucial, as a large variability in attainable improvements exists. Exploring all possible sequences of actions inevitably results in combinatorial explosion, however, and thus is not a feasible option. Furthermore, static scripts are not sufficient since their effectiveness is strongly dependent on the particular design. This paper proposes a methodology for enabling systematic and effective global optimization. The approach involves interactively and quantitatively guiding the designer's exploration pro...

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Fast prototyping of datapath-intensive architectures

Cited by 256 publications

References 10 publications

Module Selection And Data Format Conversion For Cost-optimal Dsp Synthesis

Module Selection And Data Format Conversion For Cost-optimal Dsp Synthesis

Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach

A methodology for guided behavioral-level optimization

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