2022
DOI: 10.1109/les.2021.3090029
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Fast Montgomery Modular Multiplier Using FPGAs

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Cited by 11 publications
(3 citation statements)
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“…Designs reported in [19], [20], [24], [28], and [29] are based on IM, [17], [18] is based on SP, and the rest of the listed designs are based on the MM method. In terms of computational time, [13], [14], [15], [21], [22], [23], [26], [27] are 2.93×, 4.5×, 1.72 ×, 1.02×, 1.74×, 4.58×, 1.3×, 4.3× times better but consumes 2.6×, 9.17×, 22×, 3.9×, 5.77×, 23×, 9.5×, and 24.6× more NLUTs, respectively.…”
Section: A Ffm Implementation Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…Designs reported in [19], [20], [24], [28], and [29] are based on IM, [17], [18] is based on SP, and the rest of the listed designs are based on the MM method. In terms of computational time, [13], [14], [15], [21], [22], [23], [26], [27] are 2.93×, 4.5×, 1.72 ×, 1.02×, 1.74×, 4.58×, 1.3×, 4.3× times better but consumes 2.6×, 9.17×, 22×, 3.9×, 5.77×, 23×, 9.5×, and 24.6× more NLUTs, respectively.…”
Section: A Ffm Implementation Resultsmentioning
confidence: 99%
“…Several useful modifications and related architectures have been proposed for all these three approaches [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30]. Designs reported in [14], [15], [16], [21], [22], [23], [25], [26], and [27] are based on MM, [19], [20], [24], [28], [29], [30] are based on IM and [17], [18] are using NIST recommended SP primes. Most of these designs are then further utilized in the development of several ECPM architectures [17], [19], [20], [21], [30], [31], [32], [33], [34], [35], [36], [37], [38].…”
Section: Introductionmentioning
confidence: 99%
“…Several MM and IM-based bitserial and digit-serial modular multipliers along with their FPGA implementations have been reported. In previous works, modular multipliers are based on MM 27,[43][44][45][46][47] while others are developed using the IM method. 25,29,31,33,[48][49][50][51][52] In these designs, several modifications have been introduced to reduce computational delay and hardware area occupation such as carry-save addition, residue number system (RNS), redundant sign digit (RSD) system, and even some designs utilizing built-in components of the modern FPGAs.…”
Section: Introductionmentioning
confidence: 99%