Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces

Ge, Jiancong; Ling, Ming

doi:10.1109/ispass.2019.00025

Cited by 7 publications

(6 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…3, the inputs of the model are the L2 individual RDHs and individual AAD from each core, which are obtained by Ge's model. Literatures [6] and [7] introduce how to construct the L2RDH from the L1RDH profiled from the CPU traces. Although they have not explained how to obtain AAD, we can get it easily and efficiently when profiling Hit-RDH by small updating in the information extraction code.…”

Section: Access Address Distribution(aad)mentioning

confidence: 99%

“…Before discussing these two problems, we will start from the introduction of the upstream cache model. In this paper, we choose Ge's multi-level cache model [6] [7] as the upstream cache model. The multi-level cache model proposes two new metrics, namely the Reuse-and-Stack-Transfer (RST) table and the Hit-RDH table.…”

Section: Integrating With the Upstream Cache Modelmentioning

confidence: 99%

“…In this paper, we propose a data-sharing aware shared cache miss rates model for multi-core systems with multilevel cache hierarchies. Based on the scalability of the proposed model, we integrate it with the upstream model [6] [7] that put forward by our previous work to construct a multicore multi-level cache model framework. Instead of timeconsuming multi-level cache simulations required by prior studies [3] [4], the inputs of our model can be obtained from the upstream cache model.…”

Section: Introductionmentioning

confidence: 99%

“…3. Firstly, Ge's model [6] [7] is modified and used as the upstream model to obtain each core's L2 individual Address Access Distributions, or AAD defined in section III, and individual RDHs accessing the L2 shared cache. Secondly, with considering of the coherence misses, we refine the private cache misses in the result of step 1.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Ling

Wang

et al. 2021

IEEE Access

Self Cite

View full text Add to dashboard Cite

To mitigate the ever worsening "Power wall" and "Memory wall" problems, multi-core architectures with multilevel cache hierarchies have been widely used in modern processors. However, the complexity of the architectures makes the modeling of shared caches extremely complex. In this paper, we propose a data-sharing aware analytical model for estimating the miss rates of the downstream shared cache in a multi-core environment. Moreover, the proposed model can also be integrated with upstream cache analytical models with the consideration of multi-core private cache coherent effects. The integration avoids time-consuming full simulations of the cache architecture, which are required by conventional approaches. We validate our analytical model against gem5 simulation results under 13 applications from PARSEC 2.1 benchmark suites. We compare the L2 cache miss rates with the results from gem5 under 8 hardware configurations including dual-core and quad-core architectures. The average absolute error is less than 2% for all configurations. After integrated with the upstream model, the overall average absolute error is 8.03% in 4 hardware configurations. As an application case of the integrated model, we also evaluate the miss rates of 57 different cache configurations in multi-core and multi-level cache scenarios.

show abstract

Section: Access Address Distribution(aad)mentioning

confidence: 99%

Section: Integrating With the Upstream Cache Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Ling

Wang

et al. 2021

IEEE Access

Self Cite

View full text Add to dashboard Cite

show abstract

“…[21]. To find the correlation of interference effect with memory access latency characterization of cache behavior is carried out through the reuse distance histogram model [22]. L2 cache miss rate is measured by considering L1 cache configuration as input and applying random and LRU cache replacement policies in the gem5 simulator.…”

Section: A Characterization In Isolationmentioning

confidence: 99%

Parameter Analysis of Interfering Applications in Multi-Core Environment for Throughput Enhancement

Shukla¹,

Chande²,

Ex-Director³

2019

IJEAT

View full text Add to dashboard Cite

In Multi-core systems the applications co-execute in Multi-programmed mode, have interfere with each other during execution, which creates resource bottleneck affecting the performance. To reduce the interference in a given set of resources some conventional approaches don't give guarantee of performance in a conflicting application environment. In this paper, we make an in-depth analysis of benchmark applications interference for shared resources and find out application set which could be executed adopting a designated policy to mitigate the interference effects. In this work, we have performed profiling and analysis of applications on the state-of-the-art simulator gem5. Finally, we conclude the possibility of performance improvement through the designated policy. The simulation results show the scope to have a new scheduler for performance improvement in such systems.

show abstract

Fast modeling L2 cache reuse distance histograms using combined locality information from software traces

Ling

Wang

2020

Journal of Systems Architecture

Self Cite

View full text Add to dashboard Cite

To mitigate the performance gap between the CPU and the main memory, multi-level cache architectures are widely used in modern processors. Therefore, modeling the behaviors of the downstream caches becomes a critical part of the processor performance evaluation in the early stage of Design Space Exploration (DSE). In this paper, we propose a fast and accurate L2 cache reuse distance histogram model, which can be used to predict the behaviors of the multi-level cache architectures where the L1 cache uses the LRU replacement policy and the L2 cache uses LRU/Random replacement policies. We use the L1 reuse distance histogram and two newly proposed metrics, namely the RST table and the Hit-RDH, that describing more detailed information of the software traces as the inputs. The output of our model is the L2 cache reuse distance histogram, based on which the L2 cache miss rates can be evaluated. We compare the L2 cache miss rates with the results from gem5 cycle-accurate simulations of 15 benchmarks chosen from SPEC2006. The average absolute error is less than 5%, while the evaluation time can be sped up by 7.38 times. We also extend our model into a multi-core architecture in which two cores share a unified L2 cache. The error of our model in this case is less than 7%.

show abstract

Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces

Cited by 7 publications

References 3 publications

Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence

Parameter Analysis of Interfering Applications in Multi-Core Environment for Throughput Enhancement

Fast modeling L2 cache reuse distance histograms using combined locality information from software traces

Contact Info

Product

Resources

About