Fast Integer Linear Programming Based Models for VLSI Global Routing

Behjat, Laleh; Chiang, Angie

doi:10.1109/iscas.2005.1466066

Cited by 9 publications

(4 citation statements)

References 15 publications

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“…A global router based on the concurrent techniques was presented by Behjat and Chiang [120]. The proposed technique includes an estimate of congestion in the routing area to produce high quality routes.…”

Section: B Concurrent Methods 1) Ilp-based Routingmentioning

confidence: 99%

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

et al. 2020

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Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

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Section: B Concurrent Methods 1) Ilp-based Routingmentioning

confidence: 99%

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

et al. 2020

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“…In order to globally and optimally solve the routing topology selection problem, the ILP model is adopted as our global routing engine. Although several ILP model [1] is proposed to finish the global routing task, these works only focus on minimizing total wirelength. In order to solve the routing topology selection problem while minimizing the number of changed masks, the proposed version of objective function and several added constraints are used.…”

Section: B Routing Topology Selectionmentioning

confidence: 99%

A topology-based ECO routing methodology for mask cost minimization

Bai

2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Although several Engineering Change Order (ECO) routers had been proposed to obtain a routing solution based on different design objectives, mask re-spin cost still cannot be effectively reduced because the ECO routing problem is handled in a sequential manner. This paper presents a three-stage ECO routing flow which can simultaneously route all ECO nets while considering routing layer minimization. Experimental results demonstrate that our proposed ECO routing flow can effectively reduce the number of changed masks with only negligible wirelength and via overhead.

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“…In step B, an interior point technique-based ILP solver is adopted. The complexity of the interior point ILP solver is O(z 3 ), where z is the total number of variables in the ILP formulation [17] and is given by m(5m + nl + 1). The overall computation overhead of the RDPS algorithm is O(4mnlz 3 ) for 16 samples of the β.…”

Section: Derive Task Reliability Using the Monte Carlo Simulation mentioning

confidence: 99%

Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems

Wei

Chen

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper proposes a reliability-driven task scheduling scheme for multiprocessor real-time embedded systems that optimizes system energy consumption under stochastic fault occurrences. The task scheduling problem is formulated as an integer linear program where a novel fault adaptation variable is introduced to model the uncertainties of fault occurrences. The proposed scheme, which considers both the dynamic power and the leakage power, is able to handle the scheduling of independent tasks and tasks with precedence constraints, and is capable of scheduling tasks with varying deadlines. Experimental results have demonstrated that the proposed reliability-driven parallel scheduling scheme achieves energy savings of more than 15% when compared to the approach of designing for the corner case of fault occurrences.

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Fast Integer Linear Programming Based Models for VLSI Global Routing

Cited by 9 publications

References 15 publications

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

A topology-based ECO routing methodology for mask cost minimization

Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems

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