Fast indexing for blocked array layouts to reduce cache misses

Athanasaki, Evangelia; Koziris, Nectarios

doi:10.1504/ijhpcn.2005.009429

Cited by 4 publications

(2 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…There has been significant work on runtime effects due to cache performance; however, most of this research focuses on minimizing cache misses [1,2,8,17,18,19]. By minimizing cache misses, energy spent in accessing memory is decreased, and the overall application runtime is improved.…”

Section: Related Workmentioning

confidence: 99%

Runtime adaptation

McDaniel

Hazelwood

2012

Proceedings of the 2nd International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era

View full text Add to dashboard Cite

Static alignment techniques are well studied and have been incorporated into compilers in order to optimize code locality for the instruction fetch unit in modern processors. However, current static alignment techniques have several limitations that cannot be overcome. In the exascale era, it becomes even more important to break from static techniques and develop adaptive algorithms in order to maximize the utilization of every processor cycle. In this paper, we explore those limitations and show that reactive realignment, a method where we dynamically monitor running applications, react to symptoms of poor alignment, and adapt alignment to the current execution environment and program input, is more scalable than static alignment. We present fetchesper-instruction as a runtime indicator of poor alignment. Additionally, we discuss three main opportunities that static alignment techniques cannot leverage, but which are increasingly important in large scale computing systems: microarchitectural differences of cores, dynamic program inputs that exercise different and sometimes alternating code paths, and dynamic branch behavior, including indirect branch behavior and phase changes. Finally, we will present several instances where our trigger for reactive realignment may be incorporated in practice, and discuss the limitations of dynamic alignment.

show abstract

Section: Related Workmentioning

confidence: 99%

Runtime adaptation

McDaniel

Hazelwood

2012

Proceedings of the 2nd International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era

View full text Add to dashboard Cite

show abstract

“…(2) The approach cannot support simultaneous parallel small tile access. Although other studies() have used the Z‐Morton layout to exploit 2‐D data locality and reduce conflict misses, those approaches have increased the cycle time or the access latency due to the versatility of the Morton‐index translations. In contrast, Lim and Thottethodi proposed a hardware‐based bit‐permuting unit to translate the raster scan order address to a Z‐Morton address.…”

Section: Introductionmentioning

confidence: 99%

Tile/line access cache memory based on a multi‐level Z‐order tiling data layout

Wang

Fukazawa

Kondo

et al. 2017

Concurrency and Computation

View full text Add to dashboard Cite

Summary Ineffective column‐directional cache memory access has become a bottleneck for efficient two‐dimensional (2‐D) data processing utilizing extended single instruction multiple data (SIMD) instructions. To solve this problem, we propose a cache memory with tile (column and row directions) and line (row direction) accessibility for efficient 2‐D data processing. 2‐D data access to the proposed cache memory is enabled via a hardware‐based multi‐mode address translation unit that eliminates the overhead of software‐based address calculation. To reduce the hardware overhead of the proposed cache, we propose a tag memory reduction method that replaces multiple tiles with an aligned tile set (RATS) in the cache. To verify the feasibility of the proposed cache, an LSI layout of a SIMD‐based general purpose‐oriented datapath embedding the proposed cache is designed in a 2.5×5 mm2 area using 0.18‐μm CMOS technology. Under a 3.9‐ns clock period (250 MHz), the read latency is limited to 3 clock cycles, which is the same as that for the conventional cache memory. Using the RATS method, the entire hardware overhead of the proposed cache is reduced to only 7% of that required for a conventional cache. In addition, simulation results for the proposed cache indicate a considerable reduction of L1 and L2 cache confliction misses compared with a conventional cache in power‐of‐two matrix size due to the column‐directional address stride being sufficiently smaller than page size. Therefore, the proposed cache provides efficient column‐directional parallel access as same as row‐directional parallel access so that it enables efficient SIMD operation requiring no transposition in matrix multiplication (MM). For LU decomposition (LUD), the proposed cache can provide almost the same performance to the column‐major–based LUD program as that to the row‐major–based LUD program. These results show that the proposed cache does not restrict our freedom in selecting either row‐ or column‐major order coding.

show abstract