Fast implementations of RSA cryptography

Shand, M.; Vuillemin, Jean

doi:10.1109/arith.1993.378085

Cited by 164 publications

(88 citation statements)

References 11 publications

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“…In order to keep the transponder cheap, low power and small, one of our design criteria was to avoid the use of expensive cryptographic operations (remembering that computing a modular exponentiation is O(n 2 ) in hardware [Shand and Vuillemin, 1993]), thus, we have not offered a protocol involving the merchant.…”

Section: Discussionmentioning

confidence: 99%

Parasitic Authentication

Ebringer¹,

Zheng²,

Thorne³

2000

Smart Card Research and Advanced Applications

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This paper focuses on protocols for human/smartcard interaction which allow the user to authorise individual smartcard transactions, whilst not sacrificing useability or security. In the past, protocols for secure transactions have traded off useability against security whereas the protocols presented here are designed so that they tradeoff security against hardware complexity and always give high useability. Our protocols utilise some of the concepts and assumptions present in sessional authentication, but also make improvements to this model.We do not propose the use of biometrics for authentication. Biometrics are viewed with apprehension by many users since they are irrevocable.

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Section: Discussionmentioning

confidence: 99%

Parasitic Authentication

Ebringer¹,

Zheng²,

Thorne³

2000

Smart Card Research and Advanced Applications

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“…B' := B' + 1 2b. P := ( P + A ) mod n 3. return P There are basically four general approaches for computing the product P [12][13][14][15]: Multiply and then divide, Interleaving multiplication and reduction, Brickell's method and Montgomery's method. All approaches above have a common disadvantage that it doubles up the number of bits for each multiplication and hence a large register is needed to store this result.…”

Section: B Shared Key Generatormentioning

confidence: 99%

Real-time FPGA-based Privacy and Authenticated Surveillance System

Abutaleb¹,

Allam²,

Hamdy³

et al. 2009

IJCEE

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Abstract-The detection of moving objects in a frame sequence is an essential processing component for video surveillance. The main objective of this paper is to create a prototype system that can produce secure streams, ciphertext, for every pixel in the detected moving blobs, plaintext, at a much higher rate to be applicable for real time applications. This approach can be applied in security applications such as anti-theft systems and forensic investigation systems. It could potentially be of benefit to financial investment companies, the military and security forces in order to keep certain information encrypted that no one who does not know exactly how to decrypt will not be able to obtain this information. FPGAs have been used to process larger images at faster speed because of their configuration flexibility and high data processing speed. In this paper, FPGA-based architectures for the proposed privacy and authenticated surveillance system are presented. This design can process 768x576 frame sequence at a very high bit rate that reaches to 40M bit per second in a single FPGA chip, which is adequate for most real-time vision applications.

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“…Montgomery's algorithm needs n iterations in each modular multiplication and two additions per iteration, where n is the word length. Cellular arrays based on Montgomery's algorithm can be found in [6][7][8]. In this algorithm, odd modulus is assumed.…”

Section: Introductionmentioning

confidence: 99%

RSA cryptosystem design based on the Chinese remainder theorem

Hong²,

Wu³

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

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Abstract-In this paper, we present the design and implementation of a systolic RSA cryptosystem based on a modified Montgomery's algorithm and the Chinese Remainder Theorem (CRT) technique. The CRT technique improves the throughput rate up to 4 times in the best case. The processing unit of the systolic array has 100% utilization because of the proposed block interleaving technique for multiplication and square operations in the modular exponentiation algorithm. For 512-bit inputs, the number of clock cycles needed for a modular exponentiation is about 0.13M to 0.24M. The critical path delay is 6.13ns using a 0.6µm CMOS technology. With a 150 MHz clock, we can achieve an encryption/decryption rate of about 328 to 578 Kb/s.

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Fast implementations of RSA cryptography

Cited by 164 publications

References 11 publications

Parasitic Authentication

Parasitic Authentication

Real-time FPGA-based Privacy and Authenticated Surveillance System

RSA cryptosystem design based on the Chinese remainder theorem

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