Fast hazard detection in combinational circuits

Jeong, Cheoljoo; Nowick, Steven M.

doi:10.1145/996566.996728

Cited by 6 publications

(1 citation statement)

References 13 publications

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“…This method reaches its goal by algebraically manipulating the logic function and using binary decision graphs, as presented by R. Bryant, S. Ackers, S.M. Nowick, C. Jeong, Berthomieu B. and J. Brzozowski [4][5][6][7][8][9][10][11][12]. However, this method, will not describe the hazard's evolution (at least not completely), meaning that no timing information will be revealed.…”

Section: Introductionmentioning

confidence: 99%

Novel Logic Circuits Dynamic Parameters Analysis

Galupa¹

2016

Computer Science &Amp; Information Technology ( CS &Amp; IT )

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Combinational logic circuit timing analysis is an important issue that all designers need to address. The present paper presents a simple and compact analysis procedure. We follow the guidelines drawn by previous methods, but we shall define new time-dependent logic variables that help us improve their efficiency. By using the methodology suggested, we shall replace a very laborious technique (pure delay circuit + time constants method) with a simpler procedure that can pinpoint the specific conditions for a logic circuit's anomalous behaviour within a few simple steps. Considering the logic function implemented the methodology presented will require analysis of only a limited number of situations/combinations to determine the presence of an anomalous behaviour. When anomalous behaviour is identified, the methodology provides a clear timing description.

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