Fast fractal image encoding based on adaptive search

Tong, Chong Sze; Pi, Ming Hong

doi:10.1109/83.941851

Cited by 107 publications

(61 citation statements)

References 12 publications

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“…Motivation for selecting a 2-bit quantization for s i is twofold. First, it has been advocated that, for a simple decoder, constant bit quantization should be used for scaling [17]. Furthermore, Tong shows that the optimal quantization for the scaling is a constrained uniform quantization with the last reconstruction level s l = 1.…”

Section: Software Algorithm Detailsmentioning

confidence: 99%

“…This is true even for improved methods that have been recently introduced [8,2,15,17]. To relieve the computational complexity, several searchless methods have been proposed in the literature [12,21,22,23].…”

Section: Introductionmentioning

confidence: 96%

“…Tong [17] argued that the correlation between s and g is large. Subsequently, storing the parameters based on (2) is not efficient.…”

Section: Introductionmentioning

confidence: 99%

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A hardware architecture for real-time image compression using a searchless fractal image coding method

Jackson

Ren

et al. 2007

J Real-Time Image Proc

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In this paper we present a novel hardware architecture for real-time image compression implementing a fast, searchless iterated function system (SIFS) fractal coding method. In the proposed method and corresponding hardware architecture, domain blocks are fixed to a spatially neighboring area of range blocks in a manner similar to that given by Furao and Hasegawa. A quadtree structure, covering from 32 · 32 blocks down to 2 · 2 blocks, and even to single pixels, is used for partitioning. Coding of 2 · 2 blocks and single pixels is unique among current fractal coders. The hardware architecture contains units for domain construction, zig-zag transforms, range and domain mean computation, and a parallel domain-range match capable of concurrently generating a fractal code for all quadtree levels. With this efficient, parallel hardware architecture, the fractal encoding speed is improved dramatically. Additionally, attained compression performance remains comparable to traditional searchbased and other searchless methods. Experimental results, with the proposed hardware architecture implemented on an Altera APEX20K FPGA, show that the fractal encoder can encode a 512 · 512 · 8 image in approximately 8.36 ms operating at 32.05 MHz. Therefore, this architecture is seen as a feasible solution to real-time fractal image compression.

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Section: Software Algorithm Detailsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 96%

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A hardware architecture for real-time image compression using a searchless fractal image coding method

Jackson

Ren

et al. 2007

J Real-Time Image Proc

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show abstract

“…As mentioned earlier, the luminance offset shifts the mean value of a contrast-adjusted domain block toward a range block. Hence, subtraction of the average value of domain block before contrast adjustment and addition of range mean value after intensity scaling removes the luminance offset searching problem and reduces the bias between intensity scaling and offset as described by Tong [15]. A maximum of eight bits are required for quantizing the range average value.…”

Section: Transformationmentioning

confidence: 99%

“…Tong and Pi [15] presented an adaptive search which can exclude the domain blocks that does not satisfy the necessary condition of better matching. Jacobs et al [9] skipped adjacent domain blocks to save the encoding time.…”

Section: Introductionmentioning

confidence: 99%

Low-Delay Parallel Architecture for Fractal Image Compression

Panigrahy

Chakrabarti

Dhar

2015

Circuits Syst Signal Process

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This paper presents an efficient hardware architecture for implementing fractal image compression (FIC) algorithm aimed toward image compression with improved encoding speed. The proposed architecture follows the full-search-based FIC scheme. Parallel processing has been effectively used in the present work to achieve the goal of reducing the time complexity of the encoder. This architecture requires a total of 2n + 2 clock cycles for executing the set of operations consisting of fetching the pixels, calculating the mean of range and domain blocks and doing their mapping, computing the error, and storing the fractal parameter in a memory with n number of pixels in the range block. Further, this architecture does not make use of any preprocessing operations as specified in literature and utilizes the benefits of isometric transformation without requiring additional cycles for every single matching operation. Effective application of isometric transformation has also led to memory reduction of nearly 67 %. Again, in the present work, the use of multipliers has been avoided to save the chip area, to reduce hardware complexity, and to enhance the encoding speed. The operation of transforming contracted domain block with a zero-mean domain block has facilitated relatively fast convergence at the decoder. PSNR above 30dB for a range block of size 4 × 4 has been achieved by the proposed architecture, which is comparable to that realizable by other architectures. The proposed design has been coded in Verilog HDL, has been implemented in Xilinx Virtex-5 FPGA, and operates at a clock frequency of 75.52 MHz.

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