2009 International Test Conference 2009
DOI: 10.1109/test.2009.5355668
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Fast extended test access via JTAG and FPGAs

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Cited by 14 publications
(3 citation statements)
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“…This technique was first published several years ago [1], and the technology has continued to be developed upon for each new product. Others in industry are working on having FPGAs improve test times, including enhancements to standard boundary scan methodologies [2] [3].…”
Section: Previous Workmentioning
confidence: 99%
“…This technique was first published several years ago [1], and the technology has continued to be developed upon for each new product. Others in industry are working on having FPGAs improve test times, including enhancements to standard boundary scan methodologies [2] [3].…”
Section: Previous Workmentioning
confidence: 99%
“…The approach is based on connected logic functions implemented inside the FPGA, interfacing the test bus directly to the I/O cells. This known process [2] makes it possible to implement new features on every boundary scan based system that contains an FPGA. The general approach is to implement functions inside the FPGAs programmable logic to connect higher level functionality to its I/O pins to support testing of the connected components.…”
Section: Approachmentioning
confidence: 99%
“…Moreover, reconfigurable hardware, such as Field Programmable Gate Array (FPGA) or Complex Programmable Logic Devices (CPLD), can be used to support both normal functionality as well as testing 8 . During normal operation these devices can implement the desired functionality of the system while during testing they can be configured to support specific test requirements.…”
Section: Built-in Self Test (Bist)mentioning
confidence: 99%