Fast computing of discrete cosine and sine transforms of types VI and VII

Abstract

We propose fast algorithms for computing Discrete Sine and Discrete Cosine Transforms (DCT and DST) of types VI and VII. Particular attention is paid to derivation of fast algorithms for computing DST-VII of lengths 4 and 8, which are currently under consideration for inclusion in ISO/IEC/ITU-T High Efficiency Video Coding (HEVC) standard.

Area efficient DST architectures for HEVC

“…Then, an hardware architecture for the 4-point 1D-DST, which exploits the factorization shown in [13] to reduce the number of adders and multipliers, has been proposed. Finally, two 2D-DST architectures for HEVC encoding, namely Folded and Fullparallel, have been described and implemented.…”

“…The proposed 1D-DST architecture is based on the factorization suggested in [13], which derives the N -order type-VII DST from the imaginary part of the Discrete Fourier Transform on 2N + 1 points and reduces the computational complexity from 16 multiplications and 12 additions to only 5 multiplications and 11 additions. According to [13], the 4-point HEVC-compliant DST matrix S can be decomposed by means of three sparse matrices as:…”

“…According to [13], the 4-point HEVC-compliant DST matrix S can be decomposed by means of three sparse matrices as:…”

“…Then, the second contribution is to show a novel architecture to compute the integer 4×4 1D-DST. The proposed architecture exploits the factorization in [13], which reduces the number of hardware resources with respect to the matrix-vector multiplication (MVM). Finally, the 1D-DST core is used to design two 2D-DST HEVC compliant architectures, which outperform existing DST architectures.…”

Relationship between DCT-II, DCT-VI, and DST-VII transforms

“…This question was addressed in 2011 by Chivukula and Reznik [15], who have established connection between DST-VII and DFT. This paper offers an alternative solution by establishing a mapping between DST-VII, DCT-VI, and DCT-II.…”