Fast circuit simulation on graphics processing units

Gulati,; Croix,; Khatri,; Shastry,

doi:10.1109/aspdac.2009.4796514

Cited by 56 publications

(36 citation statements)

References 9 publications

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“…[7] showed speedups of 10×-50× over a quad-core AMD CPU when using an AMD Firestream 9170 GPU (512 processors). [8] showed speedups of 32×-40× over a quadcore Intel CPU when using an NVIDIA 8800 GTX GPU (128 processors). Our approach shows a speedup of 30× for bsim3 model over a dual-core Intel Xeon processor when using an NVIDIA 9600 GT GPU with only 64 processors.…”

Section: Related Workmentioning

confidence: 99%

“…More recent work has focussed on parallelizing Model-Evaluation on GPUs. The use of GPUs for accelerating SPICE ModelEvaluation of the bsim3 model was first explored in [7] (double-precision) and subsequently in [8] (single-precision). [7] showed speedups of 10×-50× over a quad-core AMD CPU when using an AMD Firestream 9170 GPU (512 processors).…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

Kapre

DeHon

2009

2009 International Conference on Field Programmable Logic and Applications

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Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor organizations for data-parallel, floating-point computation in SPICE Model-Evaluation. Our Verilog AMS compiler produces code for parallel evaluation of non-linear circuit models suitable for use in SPICE simulations where the same model is evaluated several times for all the devices in the circuit. Our compiler uses architecture specific parallelization strategies (OpenMP for multi-core, PThreads for Cell, CUDA for GPU, statically scheduled VLIW for FPGA) when producing code for these different architectures. We automatically explore different implementation configurations (e.g. unroll factor, vector length) using our performance-tuner to identify the best possible configuration for each architecture. We demonstrate speedups of 3-182× for a Xilinx Virtex5 LX 330T, 1.3-33× for an IBM Cell, and 3-131× for an NVIDIA 9600 GT GPU over a 3 GHz Intel Xeon 5160 implementation for a variety of singleprecision device models.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

Kapre

DeHon

2009

2009 International Conference on Field Programmable Logic and Applications

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“…Xyce is a highly-parallel simulator engineered for supercomputers that demonstrates good speedups (24× on 40 processors) only on sufficiently large circuits [6]. Recently, GPUs have been used to accelerate SPICE Model-Evaluation by an impressive 10×-50× (Double-Precision evaluation in [12]) and 32×-40× (Single-Precision evaluation in [13]). Our FPGA implementation exploits a different parallelization approach and high on-chip communication and memory bandwidth to deliver an order of magnitude or greater acceleration of full, double-precision floating-point Model-Evaluation using a single FPGA without sacrificing accuracy.…”

Section: Related Workmentioning

confidence: 99%

Accelerating SPICE Model-Evaluation using FPGAs

Kapre

DeHon

2009

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

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Abstract-Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SPICE model-evaluation. Model-evaluation is a key component of the SPICE circuit simulator and it is characterized by large irregular floating-point compute graphs. We show how to exploit the parallelism available in these graphs on single-FPGA designs with a low-overhead VLIW-scheduled architecture. Our architecture uses spatial floating-point operators coupled to local high-bandwidth memories and interconnected by a time-shared network. We retime operation inputs in the model-evaluation to allow independent scheduling of computation and communication. With this approach, we demonstrate speedups of 2-18× over a dual-core 3GHz Intel Xeon 5160 when using a Xilinx Virtex 5 LX330T for a variety of SPICE device models.

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“…(3,4), since the SUM operation is linear, adding two linear/quadratic models results in a new linear/quadratic model. However, the MAX operation is non-linear, and is thus much more difficult to approximate.…”

Section: Variability-aware Design Techniquesmentioning

confidence: 99%

“…‧Look-up table models ‧Event-driven or multi-time step algorithms ‧Hierarchical simulations ‧Parallel computations The authors of [4] proposed speeding up circuit simulations using a graphics processing unit (GPU), namely the NVIDIA GeForce 8800 GTS GPU. They concentrated on the acceleration of SPICE by performing transistor model evaluations on the GPU.…”

Section: Circuit Simulation Techniquesmentioning

confidence: 99%

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

Kim

Han²,

Jewell³

2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

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Fast circuit simulation on graphics processing units

Cited by 56 publications

References 9 publications

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

Accelerating SPICE Model-Evaluation using FPGAs

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

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