Fast and robust level shifters in 65 nm CMOS

Maderbacher, Gerhard; Jackum, Thomas; Pribyl, Wolfgang; Michaelis, Sylvia; D, Michaelis; Sandner, C.

doi:10.1109/esscirc.2011.6044898

Cited by 5 publications

(2 citation statements)

References 7 publications

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“…The full‐swing level‐shifters translate from a low‐voltage swing signal to a high‐voltage swing signal [1, 2] and are typically used in output pin drivers. The floating level‐shifters shift a low‐voltage swing signal to a different reference voltage [3, 4] and are typically used to drive thin‐oxide drain‐extended MOS (DMOS) transistors in high‐voltage applications such as power converters [3], biomedical implants [5] or (as pre‐drivers) full‐swing level‐shifters [6]. The present work is concerned with the design of floating level‐shifters; we aim to show how simple design changes can give very significant power and delay reductions compared with the previously reported level‐shifters.…”

Section: Introductionmentioning

confidence: 99%

Design of fast low‐power floating high‐voltage level‐shifters

Lehmann¹

2014

Electron. lett.

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What limits performance in some recently published digital floating level-shifters are identified and a new level-shifter is proposed to address these limitations. An order-of-magnitude reduction in power dissipation compared with the recently published fast high-voltage level-shifters is obtained; simulations in a high-voltage 0.35 μm process show the proposed design is capable of shifting a 2.5 V logic signal up by 17.5 V with a propagation delay of 3 ns and a transition energy of 6 pJ.

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Section: Introductionmentioning

confidence: 99%

Design of fast low‐power floating high‐voltage level‐shifters

Lehmann¹

2014

Electron. lett.

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“…In the recent literature, there are several publications [47][48][49] that focus their attention on mitigating the contentious current consumption. There are also other circuit techniques to reduce the quiescent power in the DC steady state.…”

Section: Voltage Level Shiftermentioning

confidence: 99%

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

Kok,

Tang,

Teo

et al. 2024

Electronics

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This proposed work introduces a DC-DC converter with Switched-Capacitor Delay Deadtime Controller (SCD-DTC), Digitally Controlled Start-Up Block (DC-SUB), and Enhanced Unbalanced-Input Pair Zero-Current Detector (EUIP-ZCD) that helps to improve the overall power efficiency. It also introduces the discussion of key signal waveforms and the two major optimization flowcharts. This proposed DC-DC converter can simultaneously achieve optimized deadtime (body diode conduction < 3 ns) and almost fully eliminate the phenomenon of reverse inductor current (RIC). Furthermore, it also shows that it can achieve a well-regulated output voltage of 1.8 V with <0.01% of output ripple riding on it. All the post-layout simulation results are carried out using 0.18 µm 1P6M CMOS process using Cadence Virtuoso Spectre Circuit Simulator. The silicon chip area of our proposed work (including the output pad frame) is 1.44 mm2. The chip fabrication was sent out in January 2024 and the return of the measurement dies is expected in March 2024. The post-layout simulation results will no doubt closely resemble the measurement results since the proposed work is mostly controlled by digital blocks.

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Design of Fast-Switching Circuit Blocks

Wittmann¹

2019

Integrated High-Vin Multi-MHz Converters

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Fast and robust level shifters in 65 nm CMOS

Cited by 5 publications

References 7 publications

Design of fast low‐power floating high‐voltage level‐shifters

Design of fast low‐power floating high‐voltage level‐shifters

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

Design of Fast-Switching Circuit Blocks

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