Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

Chen, Chung-Ping; Chu, Chris; Wong, D.F.

doi:10.1145/288548.289097

Cited by 134 publications

(162 citation statements)

References 22 publications

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“…In this problem, gate sizes are allowed to be any real value between certain lower and upper bounds, and the resulting problem can be efficiently solved, for example, by using the Lagrangian relaxation technique [2]. Moreover, an optimal solution can be obtained if the underlying delay model is a posynomial function.…”

Section: Optimization Methodologymentioning

confidence: 99%

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Gate Sizing for Cell-Library-Based Designs

Ketkar

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shift, the problem of discrete gate sizing has received significantly less attention than its continuous counterpart. On the other hand, cell sizes of many realistic libraries are sparse, for example, geometrically spaced, which makes the nearest rounding approach inapplicable as large timing violations may be introduced. Therefore, it is highly desirable to design an effective algorithm to handle this discrete gate-sizing problem. Such an algorithm is proposed in this paper. The algorithm is a continuous-solution-guided dynamic-programming-like approach. A set of novel techniques, such as locality-sensitive-hashing-based solution pruning, is also proposed to accelerate the algorithm. Our experimental results demonstrate that 1) the nearest rounding approach often leads to large timing violations and 2) compared to the well-known Coudert's approach, the new algorithm saves up to 21% in area cost while still satisfying the timing constraint.

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Section: Optimization Methodologymentioning

confidence: 99%

“…Moreover, an optimal solution can be obtained if the underlying delay model is a posynomial function. For example, the solution is proven to be optimal when the Elmore delay model is used [2].…”

Section: Optimization Methodologymentioning

confidence: 99%

Gate Sizing for Cell-Library-Based Designs

Ketkar

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…For each gate i, let the area of component i as A i , P be the set of all possible paths, and n be the number of gates in circuits. The problem of minimizing the total area subject to a maximum delay bound (required time) can be formulated as [19] Minimize…”

Section: ) Mixed Ilp (Milp)mentioning

confidence: 99%

Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation

Gupta

Kahng

Kim³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Critical dimension (CD) variation caused by defocus is largely systematic with dense lines "smiling" through focus while isolated lines "frown." In this paper, we propose a new design methodology that allows explicit compensation of focus-dependent CD variation, in particular, either within a cell (self-compensated cells) or across cells in a critical path (self-compensated design). By creating iso and dense variants for each library cell, we can achieve designs that are more robust to focus variation. Optimization with a mixture of dense and iso cell variants is possible, both for area and leakage power in timing constraints (critical delay), with the latter an interesting complement to existing leakage-reduction techniques, such as dual-Vth. We implement both a heuristic and mixed-integer linear-programming (MILP) solution methods to address this optimization and experimentally compare their results. Results indicate that designing with a self-compensated cell library incurs 12% area penalty and 6% leakage increase over a baseline library while compensating for focus-dependent CD variation (i.e., the design meets timing constraints across a large range of focus variation). We observe 27% area penalty and 7% leakage increase at the worst case defocus condition using only single-pitch cells. The area penalty of circuits after using both the heuristic and MILP optimization approaches is reduced to 3% while maintaining timing. We also apply the optimization to leakage, which traditionally shows very large variability due to its exponential relationship with gate CD. We conclude that a mixed iso/dense library that is combined with a sensitivity-based optimization approach yields much better area/timing/leakage tradeoffs than using a self-compensated cell library alone. Selfcompensated designs show 25% less leakage power on average at the worst defocus condition compared to a design employing a conventional library for the benchmarks studied.

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“…There are exact solutions to the transistor-sizing problem in this context as well. However, the running time characteristics of these approaches are not well defined [3], [4]. There are studies that target different optimization goals through transistor sizing.…”

Section: Related Workmentioning

confidence: 99%

“…Sapatnekar et al proposed an optimal technique for area minimization in [3]. Yet another iterative relaxation approach with two-step optimization strategy was presented by Chen et al [4]. This method only deals with the cases where the delay is expressed in terms of Elmore delay model.…”

Section: Related Workmentioning

confidence: 99%