Fast and efficient processor allocation algorithm for torus-based chip multiprocessors

Zydek, Dawid; Selvaraj, Henry

doi:10.1016/j.compeleceng.2010.10.001

Cited by 23 publications

(23 citation statements)

References 17 publications

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“…Additionally, the hardware implementation and synthesis results of the PA for a mesh-based CMP were shown. A torus topology can be found in a recent paper by Zydek and Selvaraj (2011), where allocation techniques and their comparison to the mesh schemes are discussed. Finally, in the research by , the synthesis results of the PA driven by the schemes for a torus network are presented together with their mesh counterparts.…”

Section: Introductionmentioning

confidence: 99%

“…Other processor allocation algorithms for k-ary 2-cubes were proposed by Zydek and Selvaraj (2011). The remaining techniques, namely, SAT and SBAT, use the busy list to keep the status of nodes.…”

Section: Other Allocation Schemes For 2d-torusesmentioning

confidence: 99%

“…The BMAT technique (Zydek and Selvaraj, 2011) is based on the bit map approach used in the IFF algorithm. With respect to an incoming job, the busy array B is scanned to create a coverage array C T in the form of a bit map.…”

Section: Bit Map Allocation For Torus (Bmat)mentioning

confidence: 99%

“…The BLAT algorithm (Zydek and Selvaraj, 2011 When C J is created, each node is tested for belonging to C J , which is done by inspecting the whole C J for every node in a torus. The node which is not in the C J can be a base for the given J, otherwise, the algorithm checks another node.…”

Section: Busy List Allocation For Torus (Blat)mentioning

confidence: 99%

“…Similarly, 2D-torus networks are found in many works (Zydek and Selvaraj, 2011;. Zydek and Selvaraj (2009) presented the idea of hardware implementation of the JS and the PA, and their integration on one die together with the processing elements.…”

Section: Introductionmentioning

confidence: 99%

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Energy characteristic of a processor allocator and a network-on-chip

Zydek

Selvaraj

Borowik

et al. 2011

International Journal of Applied Mathematics and Computer Science

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Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

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Section: Introductionmentioning

confidence: 99%

Section: Other Allocation Schemes For 2d-torusesmentioning

confidence: 99%

Section: Bit Map Allocation For Torus (Bmat)mentioning

confidence: 99%

Section: Busy List Allocation For Torus (Blat)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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