Fast and effective placement and routing directed high-level synthesis for FPGAs

Zheng, Hao; Gurumani, Swathi; Rupnow, Kyle; Chen, Deming

doi:10.1145/2554688.2554775

Cited by 40 publications

(18 citation statements)

References 23 publications

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“…The MD5 example in Figure 1(c) demonstrates that even the most accurate delay estimates obtained using the post-placeand-route back-annotation approach proposed in Zheng et al [31] fails to reveal that mapping all operations into a single LUT and scheduling them within the same cycle leads to the shortest latency. In fact, such an approach would quickly converge to a sub-optimal solution, like the one in Figure 1(b).…”

Section: Discussionmentioning

confidence: 99%

“…Such an additive delay model is inaccurate in the perspective of downstream physical implementation because it does not consider mapping optimizations that are able to cluster multiple operations into a single LUT. The fact that the flow proposed in [31] focuses on the accuracy of delay estimates, while MAPS emphasizes the fundamental property of LUT mapping, [31] serves as a complement to the MAPS framework.…”

Section: Discussionmentioning

confidence: 99%

“…For example, Cong et al [10] evaluate metrics for quantifying interconnect optimization opportunity during scheduling and envision a scheduling approach that generates layout-friendly RTL architecture. Most recently, Zheng et al [31] propose an HLS flow that performs scheduling and place-and-route iteratively. By back-annotating more realistic post-place-androute delay estimates after each iteration, the HLS tool is able to compute an improved schedule for timing closure.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Tan

Dai

Gupta

et al. 2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Scheduling plays a central role in high-level synthesis, as it inserts clock boundaries into the untimed behavioral model and greatly impacts the performance, power, and area of the synthesized circuits. While current scheduling techniques can make use of pre-characterized delay values of individual operations, it is difficult to obtain accurate timing estimation on a cluster of operations without considering technology mapping. This limitation is particularly pronounced for FPGAs where a large logic network can be mapped to only a few levels of look-up tables (LUT).In this paper, we propose MAPS, a mapping-aware constrained scheduling algorithm for LUT-based FPGAs. Instead of simply summing up the estimated delay values of individual operations, MAPS jointly performs technology mapping and scheduling, creating the opportunity for more aggressive operation chaining to minimize latency and reduce area. We show that MAPS can produce a latencyoptimal solution, while supporting a variety of design timing requirements expressed in a system of difference constraints. We also present an efficient incremental scheduling technique for MAPS to effectively handle resource constraints. Experimental results with real-life benchmarks demonstrate that our proposed algorithm achieves very promising improvements in performance and resource usage when compared to a state-of-the-art commercial high-level synthesis tool targeting Xilinx FPGAs.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Tan

Dai

Gupta

et al. 2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…Additionally, this information can also be coupled with delays obtained after the place-and-route phase. This may improve the maximum frequency and the design latency and it makes the HLS results more predictable [60].…”

Section: E Hardware Resource Librarymentioning

confidence: 99%

A Survey and Evaluation of FPGA High-Level Synthesis Tools

Nane

Sima

Pilato

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

441

182

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Abstract-High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing FPGA circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set of C benchmarks, aiming at performing an in-depth evaluation in terms of performance and use of resources.

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“…Recent research has focused on integrating mapping with the upstream tool flow to explore additional optimizations in high-level analysis. In particular, Zheng et al propose a flow that iterates between upstream scheduling and downstream mapping and place-and-route and uses post-physical implementation timing for re-scheduling [23]. Most recently, Tan et al propose a constrained scheduling algorithm that considers depth-optimal LUT mapping [19].…”

Section: Related Workmentioning

confidence: 99%

Area-efficient pipelining for FPGA-targeted high-level synthesis

Zhao

Tan

Dai

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Traditional techniques for pipeline scheduling in high-level synthesis for FPGAs assume an additive delay model where each operation incurs a pre-characterized delay. While a good approximation for some operation types, this fails to consider technology mapping, where a group of logic operations can be mapped to a single lookup table (LUT) and together incur one LUT worth of delay. We propose an exact formulation of the throughput-constrained, mappingaware pipeline scheduling problem for FPGA-targeted high-level synthesis with area minimization being a primary objective. By taking this cross-layered approach, our technique is able to mitigate the pessimism inherent in static delay estimates and reduce the usage of LUTs and pipeline registers. Experimental results using our method demonstrate improved resource utilization for a number of logic-intensive, real-life benchmarks compared to a state-of-the-art commercial HLS tool for Xilinx FPGAs.

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Fast and effective placement and routing directed high-level synthesis for FPGAs

Cited by 40 publications

References 23 publications

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

A Survey and Evaluation of FPGA High-Level Synthesis Tools

Area-efficient pipelining for FPGA-targeted high-level synthesis

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