Fast and accurate resource conflict simulation for performance analysis of multi-core systems

Abstract

This work presents a SystemC-based simulation approach for fast performance analysis of parallel software components, using source code annotated with low-level timing properties. In contrast to other source-level approaches for performance analysis, timing attributes obtained from binary code can be annotated even if compiler optimizations are used without requiring changes in the compiler. To consider concurrent accesses to shared resources like caches accurately during a source-level simulation, an extension of the SystemC TLM-2.0 standard for reducing the necessary synchronization overhead is proposed as well. This enables the simulation of low-level timing effects without performing a full-fledged instruction set simulation and at speeds close to pure native execution.

Challenges of multi- and many-core architectures for electronic system-level design

“…For taking into account the timing effects of shared data and instruction memory we propose statistical models that generate timing penalties for EET blocks and load on a shared bus. This approach can also be combined with cache models, for instance based on the techniques recently presented in [20]. Especially varying cost to ensure cache coherency is an important issue and should be reflected in the (statistical) model.…”

“…These times are determined by either profiling or analysing the cross-compiled code for the target processor and back-annotated to the source code [20], [23]. In addition to EETs, OSSS enables the designer to specify local deadlines for a specific code block.…”

Fast and accurate source-level simulation of software timing considering complex code optimizations

“…Hence if one binary-level basic block is always executed before a second one, the same relation holds for their respective source-level entries in the mapping. A more detailed description of this technique can be found in [19].…”

A dynamic computation method for fast and accurate performance evaluation of multi-core architectures

“…Symbol e denotes the identity element for operator ⊗. A temporal dependency graph can still be associated to the general equations (9)- (10) and (11)- (12). The number of nodes and arcs depends on the complexity of the modeled architecture.…”

“…In case of disturbing influences such as preemption, instants are retroactively adapted during simulation. Retroactive timing correction has also been considered in [12] and [13] to overcome limitations related to the TLM-LT coding style. The method we propose is complementary to these approaches.…”